Search

Tammy J. Koontz

Examiner (ID: 17029)

Most Active Art Unit
3974
Art Unit(s)
3974, OPAP
Total Applications
2059
Issued Applications
2
Pending Applications
1
Abandoned Applications
2054

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18712545 [patent_doc_number] => 20230335178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => Word Line Delay Interlock Circuit for Write Operation [patent_app_type] => utility [patent_app_number] => 18/158489 [patent_app_country] => US [patent_app_date] => 2023-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4450 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18158489 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/158489
Word line delay interlock circuit for write operation Jan 23, 2023 Issued
Array ( [id] => 18409532 [patent_doc_number] => 20230170885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => VOLTAGE CONVERSION CIRCUIT AND MEMORY [patent_app_type] => utility [patent_app_number] => 18/157155 [patent_app_country] => US [patent_app_date] => 2023-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18157155 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/157155
Voltage conversion circuit and memory Jan 19, 2023 Issued
Array ( [id] => 19679062 [patent_doc_number] => 12190933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Refresh address generation circuit [patent_app_type] => utility [patent_app_number] => 18/153312 [patent_app_country] => US [patent_app_date] => 2023-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 35 [patent_no_of_words] => 14285 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18153312 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/153312
Refresh address generation circuit Jan 10, 2023 Issued
Array ( [id] => 19842524 [patent_doc_number] => 12254923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Nonvolatile SRAM [patent_app_type] => utility [patent_app_number] => 18/149149 [patent_app_country] => US [patent_app_date] => 2023-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 6504 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149149 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/149149
Nonvolatile SRAM Jan 1, 2023 Issued
Array ( [id] => 19733562 [patent_doc_number] => 12211562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Data erasure verification for three-dimensional non-volatile memory [patent_app_type] => utility [patent_app_number] => 18/092069 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 10758 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18092069 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/092069
Data erasure verification for three-dimensional non-volatile memory Dec 29, 2022 Issued
Array ( [id] => 18336021 [patent_doc_number] => 20230127970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => MEMORY MODULE MULTIPLE PORT BUFFER TECHNIQUES [patent_app_type] => utility [patent_app_number] => 18/087328 [patent_app_country] => US [patent_app_date] => 2022-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11190 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18087328 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/087328
Memory module multiple port buffer techniques Dec 21, 2022 Issued
Array ( [id] => 18926783 [patent_doc_number] => 20240029787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => MEMORY CONTROL CIRCUIT PROVIDING DIE-LEVEL READ RETRY TABLE, MEMORY PACKAGE, AND STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/063007 [patent_app_country] => US [patent_app_date] => 2022-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8012 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18063007 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/063007
Memory control circuit providing die-level read retry table, memory package, and storage device Dec 6, 2022 Issued
Array ( [id] => 18379416 [patent_doc_number] => 20230154505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/988797 [patent_app_country] => US [patent_app_date] => 2022-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17325 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17988797 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/988797
Page buffer circuit and memory device including the same Nov 16, 2022 Issued
Array ( [id] => 18502341 [patent_doc_number] => 20230225220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => MAGNETIC TUNNELING JUNCTION DEVICE AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/983796 [patent_app_country] => US [patent_app_date] => 2022-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17983796 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/983796
Magnetic tunneling junction device and memory device including the same Nov 8, 2022 Issued
Array ( [id] => 19811338 [patent_doc_number] => 12242732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Semiconductor apparatus with program operation control [patent_app_type] => utility [patent_app_number] => 17/983115 [patent_app_country] => US [patent_app_date] => 2022-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8318 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17983115 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/983115
Semiconductor apparatus with program operation control Nov 7, 2022 Issued
Array ( [id] => 19828572 [patent_doc_number] => 12249363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Method and apparatus for controlling refresh period of extended memory pool [patent_app_type] => utility [patent_app_number] => 17/980818 [patent_app_country] => US [patent_app_date] => 2022-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5617 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17980818 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/980818
Method and apparatus for controlling refresh period of extended memory pool Nov 3, 2022 Issued
Array ( [id] => 18194342 [patent_doc_number] => 20230047861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => MEMORY SYSTEM AND SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/976566 [patent_app_country] => US [patent_app_date] => 2022-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17976566 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/976566
Memory system and semiconductor memory device Oct 27, 2022 Issued
Array ( [id] => 19733578 [patent_doc_number] => 12211578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => DDR PHY power collapse circuit for multimode double data rate synchronous dynamic random access memory [patent_app_type] => utility [patent_app_number] => 17/973996 [patent_app_country] => US [patent_app_date] => 2022-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8014 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17973996 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/973996
DDR PHY power collapse circuit for multimode double data rate synchronous dynamic random access memory Oct 25, 2022 Issued
Array ( [id] => 19567543 [patent_doc_number] => 12142320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Memory device and method of operating the same [patent_app_type] => utility [patent_app_number] => 17/972224 [patent_app_country] => US [patent_app_date] => 2022-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12228 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17972224 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/972224
Memory device and method of operating the same Oct 23, 2022 Issued
Array ( [id] => 20189576 [patent_doc_number] => 12400698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => MRAM device with octagon profile [patent_app_type] => utility [patent_app_number] => 18/048455 [patent_app_country] => US [patent_app_date] => 2022-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 1107 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18048455 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/048455
MRAM device with octagon profile Oct 20, 2022 Issued
Array ( [id] => 20189576 [patent_doc_number] => 12400698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => MRAM device with octagon profile [patent_app_type] => utility [patent_app_number] => 18/048455 [patent_app_country] => US [patent_app_date] => 2022-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 1107 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18048455 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/048455
MRAM device with octagon profile Oct 20, 2022 Issued
Array ( [id] => 19677649 [patent_doc_number] => 12189505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Transmission of data for a machine learning operation using different microbumps [patent_app_type] => utility [patent_app_number] => 17/970183 [patent_app_country] => US [patent_app_date] => 2022-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 17859 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17970183 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/970183
Transmission of data for a machine learning operation using different microbumps Oct 19, 2022 Issued
Array ( [id] => 19654252 [patent_doc_number] => 12176052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Signal drop compensated memory [patent_app_type] => utility [patent_app_number] => 17/969269 [patent_app_country] => US [patent_app_date] => 2022-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8380 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17969269 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/969269
Signal drop compensated memory Oct 18, 2022 Issued
Array ( [id] => 18363876 [patent_doc_number] => 20230145467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => NONVOLATILE MEMORY DEVICE HAVING MULTI-STACK MEMORY BLOCK AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/045541 [patent_app_country] => US [patent_app_date] => 2022-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18045541 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/045541
Nonvolatile memory device having multi-stack memory block and method of operating the same Oct 10, 2022 Issued
Array ( [id] => 18307261 [patent_doc_number] => 20230111161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => MULTI-PROTOCOL ANALOG FRONT END CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/959833 [patent_app_country] => US [patent_app_date] => 2022-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6539 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17959833 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/959833
Multi-protocol analog front end circuit Oct 3, 2022 Issued
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