Tan Nguyen

Array ( [id] => 11020891 [patent_doc_number] => 20160217845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 14/810620 [patent_app_country] => US [patent_app_date] => 2015-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3264 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14810620 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10617423 [patent_doc_number] => 09336869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-10 [patent_title] => 'Nonvoltile resistance memory and its operation thereof' [patent_app_type] => utility [patent_app_number] => 14/809280 [patent_app_country] => US [patent_app_date] => 2015-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4303 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14809280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10689289 [patent_doc_number] => 20160035434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'MEMORY ARRAY, MEMORY DEVICE, AND METHODS FOR READING AND OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/809724 [patent_app_country] => US [patent_app_date] => 2015-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7015 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14809724 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11103632 [patent_doc_number] => 20160300602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-13 [patent_title] => 'SEMICONDUCTOR MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/807224 [patent_app_country] => US [patent_app_date] => 2015-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4886 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14807224 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11764935 [patent_doc_number] => 09373375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-21 [patent_title] => 'Non-volatile memory validity' [patent_app_type] => utility [patent_app_number] => 14/803266 [patent_app_country] => US [patent_app_date] => 2015-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4072 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14803266 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10433024 [patent_doc_number] => 20150318036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-05 [patent_title] => 'MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/799780 [patent_app_country] => US [patent_app_date] => 2015-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8439 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14799780 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10431963 [patent_doc_number] => 20150316975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-05 [patent_title] => 'FAST-WAKE MEMORY CONTROL' [patent_app_type] => utility [patent_app_number] => 14/798050 [patent_app_country] => US [patent_app_date] => 2015-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 34002 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14798050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11384269 [patent_doc_number] => 20170010325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'ADAPTIVE TEST TIME REDUCTION' [patent_app_type] => utility [patent_app_number] => 14/794635 [patent_app_country] => US [patent_app_date] => 2015-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5763 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14794635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10394452 [patent_doc_number] => 20150279459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'CONFIGURABLE REFERENCE CURRENT GENERATION FOR NON VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/740074 [patent_app_country] => US [patent_app_date] => 2015-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6614 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14740074 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10525342 [patent_doc_number] => 09251860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods' [patent_app_type] => utility [patent_app_number] => 14/735350 [patent_app_country] => US [patent_app_date] => 2015-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 10816 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14735350 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10597116 [patent_doc_number] => 09318211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Apparatuses and methods including memory array data line selection' [patent_app_type] => utility [patent_app_number] => 14/709210 [patent_app_country] => US [patent_app_date] => 2015-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 18208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14709210 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11346056 [patent_doc_number] => 09530470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Method and apparatus for pre-charging data lines in a memory cell array' [patent_app_type] => utility [patent_app_number] => 14/705717 [patent_app_country] => US [patent_app_date] => 2015-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3543 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14705717 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14521533 [patent_doc_number] => 10338017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Electric grid high impedance condition detection [patent_app_type] => utility [patent_app_number] => 14/702759 [patent_app_country] => US [patent_app_date] => 2015-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 9135 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14702759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13267631 [patent_doc_number] => 10145896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Electronic device, performance binning system and method, voltage automatic calibration system [patent_app_type] => utility [patent_app_number] => 14/695033 [patent_app_country] => US [patent_app_date] => 2015-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4738 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14695033 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10590400 [patent_doc_number] => 09312020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Methods of operating memory devices' [patent_app_type] => utility [patent_app_number] => 14/686092 [patent_app_country] => US [patent_app_date] => 2015-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6588 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14686092 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10328859 [patent_doc_number] => 20150213863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'SUB-BLOCK DISABLING IN 3D MEMORY' [patent_app_type] => utility [patent_app_number] => 14/682762 [patent_app_country] => US [patent_app_date] => 2015-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14682762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10328887 [patent_doc_number] => 20150213891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'METHODS AND APPARATUSES FOR PROGRAMMING MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 14/679781 [patent_app_country] => US [patent_app_date] => 2015-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8356 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14679781 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10665105 [patent_doc_number] => 20160011249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'SYSTEMS AND METHODS FOR DETECTING AND IDENTIFYING ARCING BASED ON NUMERICAL ANALYSIS' [patent_app_type] => utility [patent_app_number] => 14/675012 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5988 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14675012 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11366884 [patent_doc_number] => 20170004865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 15/125658 [patent_app_country] => US [patent_app_date] => 2015-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 28246 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15125658 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11764955 [patent_doc_number] => 09373395 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-06-21 [patent_title] => 'Apparatus to reduce retention failure in complementary resistive memory' [patent_app_type] => utility [patent_app_number] => 14/638942 [patent_app_country] => US [patent_app_date] => 2015-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8694 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14638942 [rel_patent_id] =>[rel_patent_doc_number] =>)