
Tan Nguyen
Examiner (ID: 11472, Phone: (571)272-1789 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 3103, 2818, 2309, 2827 |
| Total Applications | 3340 |
| Issued Applications | 3151 |
| Pending Applications | 45 |
| Abandoned Applications | 149 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17971386
[patent_doc_number] => 11488935
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-11-01
[patent_title] => Scalable network-on-package for connecting chiplet-based designs
[patent_app_type] => utility
[patent_app_number] => 17/314857
[patent_app_country] => US
[patent_app_date] => 2021-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8621
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17314857
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/314857 | Scalable network-on-package for connecting chiplet-based designs | May 6, 2021 | Issued |
Array
(
[id] => 17173832
[patent_doc_number] => 20210327503
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-21
[patent_title] => NON-VOLATILE MEMORY DEVICE WITH CONCURRENT BANK OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 17/246190
[patent_app_country] => US
[patent_app_date] => 2021-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15542
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17246190
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/246190 | Non-volatile memory device with concurrent bank operations | Apr 29, 2021 | Issued |
Array
(
[id] => 17099274
[patent_doc_number] => 20210287065
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-16
[patent_title] => OUTPUT CIRCUITRY FOR NON-VOLATILE MEMORY ARRAY IN NEURAL NETWORK
[patent_app_type] => utility
[patent_app_number] => 17/238077
[patent_app_country] => US
[patent_app_date] => 2021-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7829
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -37
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17238077
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/238077 | Output circuitry for non-volatile memory array in neural network | Apr 21, 2021 | Issued |
Array
(
[id] => 18688404
[patent_doc_number] => 11784149
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2023-10-10
[patent_title] => Chip bump interface compatible with different orientations and types of devices
[patent_app_type] => utility
[patent_app_number] => 17/235843
[patent_app_country] => US
[patent_app_date] => 2021-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 20
[patent_no_of_words] => 7401
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17235843
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/235843 | Chip bump interface compatible with different orientations and types of devices | Apr 19, 2021 | Issued |
Array
(
[id] => 17551327
[patent_doc_number] => 20220122669
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-21
[patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/235282
[patent_app_country] => US
[patent_app_date] => 2021-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16906
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17235282
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/235282 | Memory device and method of operating the same | Apr 19, 2021 | Issued |
Array
(
[id] => 17825575
[patent_doc_number] => 11430527
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-08-30
[patent_title] => Method for performing operation in memory device
[patent_app_type] => utility
[patent_app_number] => 17/233590
[patent_app_country] => US
[patent_app_date] => 2021-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 17
[patent_no_of_words] => 3720
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17233590
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/233590 | Method for performing operation in memory device | Apr 18, 2021 | Issued |
Array
(
[id] => 18156256
[patent_doc_number] => 11569250
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-31
[patent_title] => Ferroelectric memory device using back-end-of-line (BEOL) thin film access transistors and methods for forming the same
[patent_app_type] => utility
[patent_app_number] => 17/230598
[patent_app_country] => US
[patent_app_date] => 2021-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 13702
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17230598
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/230598 | Ferroelectric memory device using back-end-of-line (BEOL) thin film access transistors and methods for forming the same | Apr 13, 2021 | Issued |
Array
(
[id] => 18828922
[patent_doc_number] => 11844223
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2023-12-12
[patent_title] => Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging
[patent_app_type] => utility
[patent_app_number] => 17/229750
[patent_app_country] => US
[patent_app_date] => 2021-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 55
[patent_figures_cnt] => 59
[patent_no_of_words] => 28829
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17229750
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/229750 | Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging | Apr 12, 2021 | Issued |
Array
(
[id] => 17551331
[patent_doc_number] => 20220122673
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-21
[patent_title] => MEMORY DEVICE INCLUDING PASS TRANSISTOR CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 17/227501
[patent_app_country] => US
[patent_app_date] => 2021-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14639
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17227501
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/227501 | Memory device including pass transistor circuit | Apr 11, 2021 | Issued |
Array
(
[id] => 17174230
[patent_doc_number] => 20210327901
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-21
[patent_title] => MEMORY CELL CIRCUIT, MEMORY CELL ARRANGEMENT, AND METHODS THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/224185
[patent_app_country] => US
[patent_app_date] => 2021-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 24458
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224185
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/224185 | Memory cell circuit, memory cell arrangement, and methods thereof | Apr 6, 2021 | Issued |
Array
(
[id] => 17025547
[patent_doc_number] => 20210249419
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-12
[patent_title] => MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/222740
[patent_app_country] => US
[patent_app_date] => 2021-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13952
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17222740
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/222740 | Memory devices and methods of manufacturing thereof | Apr 4, 2021 | Issued |
Array
(
[id] => 18073512
[patent_doc_number] => 11532349
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-20
[patent_title] => Power distribution for stacked memory
[patent_app_type] => utility
[patent_app_number] => 17/221498
[patent_app_country] => US
[patent_app_date] => 2021-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 17552
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17221498
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/221498 | Power distribution for stacked memory | Apr 1, 2021 | Issued |
Array
(
[id] => 17862649
[patent_doc_number] => 11443810
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-13
[patent_title] => Negative level shifters and nonvolatile memory devices including the same
[patent_app_type] => utility
[patent_app_number] => 17/220368
[patent_app_country] => US
[patent_app_date] => 2021-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 24
[patent_no_of_words] => 14789
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17220368
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/220368 | Negative level shifters and nonvolatile memory devices including the same | Mar 31, 2021 | Issued |
Array
(
[id] => 17523140
[patent_doc_number] => 20220108989
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-07
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/219175
[patent_app_country] => US
[patent_app_date] => 2021-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14310
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219175
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/219175 | Semiconductor device | Mar 30, 2021 | Issued |
Array
(
[id] => 17917234
[patent_doc_number] => 20220319630
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-06
[patent_title] => ERROR AVOIDANCE BASED ON VOLTAGE DISTRIBUTION PARAMETERS OF BLOCK FAMILIES
[patent_app_type] => utility
[patent_app_number] => 17/217780
[patent_app_country] => US
[patent_app_date] => 2021-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22690
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17217780
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/217780 | Error avoidance based on voltage distribution parameters of block families | Mar 29, 2021 | Issued |
Array
(
[id] => 17901246
[patent_doc_number] => 20220310908
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-29
[patent_title] => REVERSIBLE RESISTIVE MEMORY LOGIC GATE DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/216622
[patent_app_country] => US
[patent_app_date] => 2021-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4463
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17216622
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/216622 | Reversible resistive memory logic gate device | Mar 28, 2021 | Issued |
Array
(
[id] => 16951456
[patent_doc_number] => 20210210148
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-08
[patent_title] => MEMORY SYSTEM AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/210732
[patent_app_country] => US
[patent_app_date] => 2021-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10734
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17210732
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/210732 | MEMORY SYSTEM AND OPERATING METHOD THEREOF | Mar 23, 2021 | Abandoned |
Array
(
[id] => 17971106
[patent_doc_number] => 11488653
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-01
[patent_title] => Power supply system and semiconductor package assembly
[patent_app_type] => utility
[patent_app_number] => 17/211693
[patent_app_country] => US
[patent_app_date] => 2021-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 18
[patent_no_of_words] => 7597
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17211693
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/211693 | Power supply system and semiconductor package assembly | Mar 23, 2021 | Issued |
Array
(
[id] => 17699981
[patent_doc_number] => 11373713
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-06-28
[patent_title] => Memory control method, memory storage device, and memory control circuit unit
[patent_app_type] => utility
[patent_app_number] => 17/209214
[patent_app_country] => US
[patent_app_date] => 2021-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 11222
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17209214
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/209214 | Memory control method, memory storage device, and memory control circuit unit | Mar 21, 2021 | Issued |
Array
(
[id] => 18120355
[patent_doc_number] => 11551753
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-10
[patent_title] => Three-dimensional memory device with embedded dynamic random-access memory
[patent_app_type] => utility
[patent_app_number] => 17/207258
[patent_app_country] => US
[patent_app_date] => 2021-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 15
[patent_no_of_words] => 11773
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17207258
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/207258 | Three-dimensional memory device with embedded dynamic random-access memory | Mar 18, 2021 | Issued |