Search

Tan V. Mai

Examiner (ID: 15743)

Most Active Art Unit
2193
Art Unit(s)
2306, 2193, 2787, 2786, 2121, 2124, 2302, 2301, 2182, 2183
Total Applications
3863
Issued Applications
3431
Pending Applications
94
Abandoned Applications
349

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6684830 [patent_doc_number] => 20030120694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Method and apparatus for use in booth-encoded multiplication' [patent_app_type] => new [patent_app_number] => 10/039867 [patent_app_country] => US [patent_app_date] => 2001-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8586 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20030120694.pdf [firstpage_image] =>[orig_patent_app_number] => 10039867 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/039867
Method and apparatus for use in booth-encoded multiplication Dec 19, 2001 Issued
Array ( [id] => 7611395 [patent_doc_number] => 06904447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'High speed low power 4-2 compressor' [patent_app_type] => utility [patent_app_number] => 10/023686 [patent_app_country] => US [patent_app_date] => 2001-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5707 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/904/06904447.pdf [firstpage_image] =>[orig_patent_app_number] => 10023686 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/023686
High speed low power 4-2 compressor Dec 17, 2001 Issued
Array ( [id] => 921700 [patent_doc_number] => 07325025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-29 [patent_title] => 'Look-ahead carry adder circuit' [patent_app_type] => utility [patent_app_number] => 10/020447 [patent_app_country] => US [patent_app_date] => 2001-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9424 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/325/07325025.pdf [firstpage_image] =>[orig_patent_app_number] => 10020447 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/020447
Look-ahead carry adder circuit Dec 17, 2001 Issued
Array ( [id] => 507575 [patent_doc_number] => 07209938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-24 [patent_title] => 'Kalman filter with adaptive measurement variance estimator' [patent_app_type] => utility [patent_app_number] => 10/023346 [patent_app_country] => US [patent_app_date] => 2001-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5927 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/209/07209938.pdf [firstpage_image] =>[orig_patent_app_number] => 10023346 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/023346
Kalman filter with adaptive measurement variance estimator Dec 16, 2001 Issued
Array ( [id] => 5910242 [patent_doc_number] => 20020143839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Computer method and apparatus for division and square root operations using signed digit' [patent_app_type] => new [patent_app_number] => 10/016902 [patent_app_country] => US [patent_app_date] => 2001-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9676 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20020143839.pdf [firstpage_image] =>[orig_patent_app_number] => 10016902 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/016902
Computer method and apparatus for division and square root operations using signed digit Dec 13, 2001 Issued
Array ( [id] => 1124565 [patent_doc_number] => 06799193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-28 [patent_title] => 'Fully digital symbol synchronization technique' [patent_app_type] => B2 [patent_app_number] => 10/022465 [patent_app_country] => US [patent_app_date] => 2001-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3663 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/799/06799193.pdf [firstpage_image] =>[orig_patent_app_number] => 10022465 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/022465
Fully digital symbol synchronization technique Dec 13, 2001 Issued
Array ( [id] => 704696 [patent_doc_number] => 07069283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'Method and circuit for calculating multiple of unit value and generating a periodic function' [patent_app_type] => utility [patent_app_number] => 10/014575 [patent_app_country] => US [patent_app_date] => 2001-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 5211 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/069/07069283.pdf [firstpage_image] =>[orig_patent_app_number] => 10014575 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/014575
Method and circuit for calculating multiple of unit value and generating a periodic function Dec 13, 2001 Issued
Array ( [id] => 1030484 [patent_doc_number] => 06883012 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-19 [patent_title] => 'Linear-to-log converter for power estimation in a wireless data network receiver' [patent_app_type] => utility [patent_app_number] => 10/015486 [patent_app_country] => US [patent_app_date] => 2001-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3966 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/883/06883012.pdf [firstpage_image] =>[orig_patent_app_number] => 10015486 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/015486
Linear-to-log converter for power estimation in a wireless data network receiver Dec 10, 2001 Issued
Array ( [id] => 6736825 [patent_doc_number] => 20030014460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'Analog filter' [patent_app_type] => new [patent_app_number] => 10/203004 [patent_app_country] => US [patent_app_date] => 2002-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7678 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20030014460.pdf [firstpage_image] =>[orig_patent_app_number] => 10203004 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/203004
Analog filter suitable for smoothing a ΔΣ-modulated signal Dec 5, 2001 Issued
Array ( [id] => 6211255 [patent_doc_number] => 20020073126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Device for determining the rank of a sample, an apparatus for determining the rank of a plurality of samples, and the ith rank ordered filter' [patent_app_type] => new [patent_app_number] => 10/011877 [patent_app_country] => US [patent_app_date] => 2001-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5607 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20020073126.pdf [firstpage_image] =>[orig_patent_app_number] => 10011877 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/011877
Device for determining the rank of a sample, an apparatus for determining the rank of a plurality of samples, and the ith rank ordered filter Dec 2, 2001 Issued
Array ( [id] => 1133662 [patent_doc_number] => 06792444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Filter devices and methods' [patent_app_type] => B2 [patent_app_number] => 10/015706 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 6876 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/792/06792444.pdf [firstpage_image] =>[orig_patent_app_number] => 10015706 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/015706
Filter devices and methods Nov 29, 2001 Issued
Array ( [id] => 6866259 [patent_doc_number] => 20030191785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-09 [patent_title] => 'Single-channel convolution in a vector processing computer system' [patent_app_type] => new [patent_app_number] => 09/996877 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5615 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20030191785.pdf [firstpage_image] =>[orig_patent_app_number] => 09996877 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/996877
Single-channel convolution in a vector processing computer system Nov 29, 2001 Issued
Array ( [id] => 6654874 [patent_doc_number] => 20030105789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-05 [patent_title] => 'Solving systems of nonlinear equations using interval arithmetic and term consistency' [patent_app_type] => new [patent_app_number] => 09/996227 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7418 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20030105789.pdf [firstpage_image] =>[orig_patent_app_number] => 09996227 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/996227
Solving systems of nonlinear equations using interval arithmetic and term consistency Nov 29, 2001 Abandoned
Array ( [id] => 6766807 [patent_doc_number] => 20030101207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'Random carry-in for floating-point operations' [patent_app_type] => new [patent_app_number] => 09/999135 [patent_app_country] => US [patent_app_date] => 2001-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5757 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20030101207.pdf [firstpage_image] =>[orig_patent_app_number] => 09999135 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/999135
Random carry-in for floating-point operations Nov 28, 2001 Issued
Array ( [id] => 1082900 [patent_doc_number] => 06836783 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-28 [patent_title] => 'Finite-difference solver based on field programmable interconnect devices' [patent_app_type] => B1 [patent_app_number] => 09/683136 [patent_app_country] => US [patent_app_date] => 2001-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 4348 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/836/06836783.pdf [firstpage_image] =>[orig_patent_app_number] => 09683136 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/683136
Finite-difference solver based on field programmable interconnect devices Nov 25, 2001 Issued
Array ( [id] => 6458827 [patent_doc_number] => 20020178196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Modular arithmetic coprocessor comprising two multiplication circuits working in parallel' [patent_app_type] => new [patent_app_number] => 09/991494 [patent_app_country] => US [patent_app_date] => 2001-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 14910 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20020178196.pdf [firstpage_image] =>[orig_patent_app_number] => 09991494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/991494
Modular arithmetic coprocessor comprising two multiplication circuits working in parallel Nov 20, 2001 Abandoned
Array ( [id] => 6802227 [patent_doc_number] => 20030097392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Four-rail NCL incrementor/decrementor' [patent_app_type] => new [patent_app_number] => 09/989107 [patent_app_country] => US [patent_app_date] => 2001-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7841 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20030097392.pdf [firstpage_image] =>[orig_patent_app_number] => 09989107 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/989107
Four-rail NCL incrementor/decrementor Nov 20, 2001 Abandoned
Array ( [id] => 6551026 [patent_doc_number] => 20020194235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Processing apparatus' [patent_app_type] => new [patent_app_number] => 09/988615 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5200 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20020194235.pdf [firstpage_image] =>[orig_patent_app_number] => 09988615 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/988615
Processing apparatus Nov 19, 2001 Issued
Array ( [id] => 6368192 [patent_doc_number] => 20020059355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Method and apparatus for performing multiply-add operations on packed data' [patent_app_type] => new [patent_app_number] => 09/989736 [patent_app_country] => US [patent_app_date] => 2001-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8774 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20020059355.pdf [firstpage_image] =>[orig_patent_app_number] => 09989736 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/989736
Method and apparatus for performing multiply-add operations on packed data Nov 18, 2001 Issued
Array ( [id] => 6670249 [patent_doc_number] => 20030115233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Performance optimized approach for efficient downsampling operations' [patent_app_type] => new [patent_app_number] => 09/989857 [patent_app_country] => US [patent_app_date] => 2001-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8198 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20030115233.pdf [firstpage_image] =>[orig_patent_app_number] => 09989857 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/989857
Performance optimized approach for efficient downsampling operations Nov 18, 2001 Issued
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