Search

Tan V. Mai

Examiner (ID: 15743)

Most Active Art Unit
2193
Art Unit(s)
2306, 2193, 2787, 2786, 2121, 2124, 2302, 2301, 2182, 2183
Total Applications
3863
Issued Applications
3431
Pending Applications
94
Abandoned Applications
349

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 957979 [patent_doc_number] => 06957243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-18 [patent_title] => 'Block-serial finite field multipliers' [patent_app_type] => utility [patent_app_number] => 09/973617 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3867 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/957/06957243.pdf [firstpage_image] =>[orig_patent_app_number] => 09973617 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/973617
Block-serial finite field multipliers Oct 8, 2001 Issued
Array ( [id] => 6085012 [patent_doc_number] => 20020083107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Fast fourier transform processor using high speed area-efficient algorithm' [patent_app_type] => new [patent_app_number] => 09/970695 [patent_app_country] => US [patent_app_date] => 2001-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2436 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20020083107.pdf [firstpage_image] =>[orig_patent_app_number] => 09970695 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/970695
Fast fourier transform processor using high speed area-efficient algorithm Oct 4, 2001 Abandoned
Array ( [id] => 6551054 [patent_doc_number] => 20020194237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Circuit and method for performing multiple modulo mathematic operations' [patent_app_type] => new [patent_app_number] => 09/971325 [patent_app_country] => US [patent_app_date] => 2001-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9677 [patent_no_of_claims] => 77 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20020194237.pdf [firstpage_image] =>[orig_patent_app_number] => 09971325 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/971325
Circuit and method for performing multiple modulo mathematic operations Oct 3, 2001 Issued
Array ( [id] => 469108 [patent_doc_number] => 07240083 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-07-03 [patent_title] => 'Precision complex sinusoid generation using limited processing' [patent_app_type] => utility [patent_app_number] => 09/966103 [patent_app_country] => US [patent_app_date] => 2001-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5591 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/240/07240083.pdf [firstpage_image] =>[orig_patent_app_number] => 09966103 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/966103
Precision complex sinusoid generation using limited processing Sep 30, 2001 Issued
Array ( [id] => 1088406 [patent_doc_number] => 06832231 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-14 [patent_title] => 'Multiple width random number generation' [patent_app_type] => B1 [patent_app_number] => 09/966967 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2945 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/832/06832231.pdf [firstpage_image] =>[orig_patent_app_number] => 09966967 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/966967
Multiple width random number generation Sep 27, 2001 Issued
Array ( [id] => 1196667 [patent_doc_number] => 06732133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-04 [patent_title] => 'Montgomery multiplier with dual independent channels' [patent_app_type] => B2 [patent_app_number] => 09/965915 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7306 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732133.pdf [firstpage_image] =>[orig_patent_app_number] => 09965915 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/965915
Montgomery multiplier with dual independent channels Sep 27, 2001 Issued
Array ( [id] => 1310726 [patent_doc_number] => 06625631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-23 [patent_title] => 'Component reduction in montgomery multiplier processing element' [patent_app_type] => B2 [patent_app_number] => 09/966044 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6069 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625631.pdf [firstpage_image] =>[orig_patent_app_number] => 09966044 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/966044
Component reduction in montgomery multiplier processing element Sep 27, 2001 Issued
Array ( [id] => 7623931 [patent_doc_number] => 06725246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-20 [patent_title] => 'Method and apparatus for varying-radix numeration system' [patent_app_type] => B2 [patent_app_number] => 09/964957 [patent_app_country] => US [patent_app_date] => 2001-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4223 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/725/06725246.pdf [firstpage_image] =>[orig_patent_app_number] => 09964957 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/964957
Method and apparatus for varying-radix numeration system Sep 26, 2001 Issued
Array ( [id] => 1184352 [patent_doc_number] => 06748412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-08 [patent_title] => 'Square-and-multiply exponent processor' [patent_app_type] => B2 [patent_app_number] => 09/964137 [patent_app_country] => US [patent_app_date] => 2001-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5977 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/748/06748412.pdf [firstpage_image] =>[orig_patent_app_number] => 09964137 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/964137
Square-and-multiply exponent processor Sep 25, 2001 Issued
Array ( [id] => 6630490 [patent_doc_number] => 20020065860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Data processing apparatus and method for saturating data values' [patent_app_type] => new [patent_app_number] => 09/957467 [patent_app_country] => US [patent_app_date] => 2001-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11412 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20020065860.pdf [firstpage_image] =>[orig_patent_app_number] => 09957467 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/957467
Data processing apparatus and method for saturating data values Sep 19, 2001 Abandoned
Array ( [id] => 949874 [patent_doc_number] => 06963887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-08 [patent_title] => 'Method and device for performing data pattern matching' [patent_app_type] => utility [patent_app_number] => 09/956775 [patent_app_country] => US [patent_app_date] => 2001-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4100 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/963/06963887.pdf [firstpage_image] =>[orig_patent_app_number] => 09956775 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/956775
Method and device for performing data pattern matching Sep 18, 2001 Issued
Array ( [id] => 704703 [patent_doc_number] => 07069287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'Method for efficient computation of odd characteristic extension fields' [patent_app_type] => utility [patent_app_number] => 09/956755 [patent_app_country] => US [patent_app_date] => 2001-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10761 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/069/07069287.pdf [firstpage_image] =>[orig_patent_app_number] => 09956755 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/956755
Method for efficient computation of odd characteristic extension fields Sep 18, 2001 Issued
Array ( [id] => 5937647 [patent_doc_number] => 20020062329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-23 [patent_title] => 'Analog fir filter with parallel interleaved architecture' [patent_app_type] => new [patent_app_number] => 09/957137 [patent_app_country] => US [patent_app_date] => 2001-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3477 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20020062329.pdf [firstpage_image] =>[orig_patent_app_number] => 09957137 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/957137
Analog fir filter with parallel interleaved architecture Sep 18, 2001 Issued
Array ( [id] => 6722162 [patent_doc_number] => 20030055852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Reconfigurable arithmetic logic block array for FPGAs' [patent_app_type] => new [patent_app_number] => 09/957147 [patent_app_country] => US [patent_app_date] => 2001-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5733 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20030055852.pdf [firstpage_image] =>[orig_patent_app_number] => 09957147 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/957147
Reconfigurable arithmetic logic block array for FPGAs Sep 18, 2001 Abandoned
Array ( [id] => 777671 [patent_doc_number] => 07003545 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-21 [patent_title] => 'High performance carry chain with reduced macrocell logic and fast carry lookahead' [patent_app_type] => utility [patent_app_number] => 09/951685 [patent_app_country] => US [patent_app_date] => 2001-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7345 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/003/07003545.pdf [firstpage_image] =>[orig_patent_app_number] => 09951685 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/951685
High performance carry chain with reduced macrocell logic and fast carry lookahead Sep 10, 2001 Issued
Array ( [id] => 6558663 [patent_doc_number] => 20020138535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'SIMD sum of product arithmetic method and circuit, and semiconductor integrated circuit device equipped with the SIMD sum of product arithmetic circuit' [patent_app_type] => new [patent_app_number] => 09/945697 [patent_app_country] => US [patent_app_date] => 2001-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6529 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20020138535.pdf [firstpage_image] =>[orig_patent_app_number] => 09945697 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/945697
SIMD sum of product arithmetic method and circuit, and semiconductor integrated circuit device equipped with the SIMD sum of product arithmetic circuit Sep 4, 2001 Issued
Array ( [id] => 6751799 [patent_doc_number] => 20030046320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Calculator device' [patent_app_type] => new [patent_app_number] => 09/941577 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1271 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20030046320.pdf [firstpage_image] =>[orig_patent_app_number] => 09941577 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/941577
Calculator device for enabling a keypad to function as both a keypad and a calculator Aug 29, 2001 Issued
Array ( [id] => 6127003 [patent_doc_number] => 20020075975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Addition circuit for digital data' [patent_app_type] => new [patent_app_number] => 09/935791 [patent_app_country] => US [patent_app_date] => 2001-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2668 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20020075975.pdf [firstpage_image] =>[orig_patent_app_number] => 09935791 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/935791
Addition circuit for digital data with a delayed saturation operation for the most significant data bits Aug 21, 2001 Issued
Array ( [id] => 6483331 [patent_doc_number] => 20020152253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-17 [patent_title] => 'System and method for adaptive filtering' [patent_app_type] => new [patent_app_number] => 09/933004 [patent_app_country] => US [patent_app_date] => 2001-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5525 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20020152253.pdf [firstpage_image] =>[orig_patent_app_number] => 09933004 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/933004
System and method for adaptive filtering Aug 20, 2001 Issued
Array ( [id] => 5910252 [patent_doc_number] => 20020143841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Multiplexer based parallel n-bit adder circuit for high speed processing' [patent_app_type] => new [patent_app_number] => 09/933623 [patent_app_country] => US [patent_app_date] => 2001-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7736 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20020143841.pdf [firstpage_image] =>[orig_patent_app_number] => 09933623 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/933623
Multiplexer based parallel n-bit adder circuit for high speed processing Aug 19, 2001 Abandoned
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