Tan V. Mai

Array ( [id] => 1084961 [patent_doc_number] => 06834293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-21 [patent_title] => 'Vector scaling system for G.728 annex G' [patent_app_type] => B2 [patent_app_number] => 09/882766 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4099 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/834/06834293.pdf [firstpage_image] =>[orig_patent_app_number] => 09882766 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1154400 [patent_doc_number] => 06779005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-17 [patent_title] => 'Method and device for detecting random missing code' [patent_app_type] => B2 [patent_app_number] => 09/876824 [patent_app_country] => US [patent_app_date] => 2001-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 1666 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/779/06779005.pdf [firstpage_image] =>[orig_patent_app_number] => 09876824 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1149131 [patent_doc_number] => 06782405 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-24 [patent_title] => 'Method and apparatus for performing division and square root functions using a multiplier and a multipartite table' [patent_app_type] => B1 [patent_app_number] => 09/876786 [patent_app_country] => US [patent_app_date] => 2001-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 10597 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/782/06782405.pdf [firstpage_image] =>[orig_patent_app_number] => 09876786 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1149134 [patent_doc_number] => 06782406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-24 [patent_title] => 'Fast CMOS adder with null-carry look-ahead' [patent_app_type] => B2 [patent_app_number] => 09/877805 [patent_app_country] => US [patent_app_date] => 2001-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 4631 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/782/06782406.pdf [firstpage_image] =>[orig_patent_app_number] => 09877805 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 933137 [patent_doc_number] => 06981012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-27 [patent_title] => 'Method and circuit for normalization of floating point significants in a SIMD array MPP' [patent_app_type] => utility [patent_app_number] => 09/874044 [patent_app_country] => US [patent_app_date] => 2001-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4340 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/981/06981012.pdf [firstpage_image] =>[orig_patent_app_number] => 09874044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6551081 [patent_doc_number] => 20020194238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Method and circuit for alignment of floating point significands in a SIMD array MPP' [patent_app_type] => new [patent_app_number] => 09/874307 [patent_app_country] => US [patent_app_date] => 2001-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5191 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20020194238.pdf [firstpage_image] =>[orig_patent_app_number] => 09874307 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6988451 [patent_doc_number] => 20010037352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Multiplier capable of multiplication of large multiplicands and parallel multiplications small multiplicands' [patent_app_type] => new [patent_app_number] => 09/874525 [patent_app_country] => US [patent_app_date] => 2001-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4040 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20010037352.pdf [firstpage_image] =>[orig_patent_app_number] => 09874525 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6558732 [patent_doc_number] => 20020138540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Multiplier circuit' [patent_app_type] => new [patent_app_number] => 09/873760 [patent_app_country] => US [patent_app_date] => 2001-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 44513 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20020138540.pdf [firstpage_image] =>[orig_patent_app_number] => 09873760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6551116 [patent_doc_number] => 20020194239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Floating point overflow and sign detection' [patent_app_type] => new [patent_app_number] => 09/873744 [patent_app_country] => US [patent_app_date] => 2001-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6231 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20020194239.pdf [firstpage_image] =>[orig_patent_app_number] => 09873744 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1192127 [patent_doc_number] => 06735607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-11 [patent_title] => 'Transparent data access and interpolation apparatus and method therefor' [patent_app_type] => B2 [patent_app_number] => 09/872206 [patent_app_country] => US [patent_app_date] => 2001-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6721 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735607.pdf [firstpage_image] =>[orig_patent_app_number] => 09872206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6835955 [patent_doc_number] => 20030163501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Implementation to avoid overflow in IIR filter' [patent_app_type] => new [patent_app_number] => 09/870026 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3195 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20030163501.pdf [firstpage_image] =>[orig_patent_app_number] => 09870026 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6757240 [patent_doc_number] => 20030005017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Simultaneous dual rail static carry-save-adder circuit' [patent_app_type] => new [patent_app_number] => 09/864137 [patent_app_country] => US [patent_app_date] => 2001-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7241 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20030005017.pdf [firstpage_image] =>[orig_patent_app_number] => 09864137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 957981 [patent_doc_number] => 06957244 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-18 [patent_title] => 'Reduced-width low-error multiplier' [patent_app_type] => utility [patent_app_number] => 09/861555 [patent_app_country] => US [patent_app_date] => 2001-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6093 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/957/06957244.pdf [firstpage_image] =>[orig_patent_app_number] => 09861555 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5990041 [patent_doc_number] => 20020099751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Energy saving multiplication device and method' [patent_app_type] => new [patent_app_number] => 09/861572 [patent_app_country] => US [patent_app_date] => 2001-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5413 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20020099751.pdf [firstpage_image] =>[orig_patent_app_number] => 09861572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6114785 [patent_doc_number] => 20020174155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Method for calculating arithmetic inverse over finite fields for use in cryptography' [patent_app_type] => new [patent_app_number] => 09/859244 [patent_app_country] => US [patent_app_date] => 2001-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7369 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20020174155.pdf [firstpage_image] =>[orig_patent_app_number] => 09859244 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1185535 [patent_doc_number] => 06745219 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Arithmetic unit using stochastic data processing' [patent_app_type] => B1 [patent_app_number] => 09/853747 [patent_app_country] => US [patent_app_date] => 2001-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4800 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/745/06745219.pdf [firstpage_image] =>[orig_patent_app_number] => 09853747 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1180397 [patent_doc_number] => 06754684 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Method and apparatus for median filter on SIMD architecture digital data processor' [patent_app_type] => B1 [patent_app_number] => 09/853874 [patent_app_country] => US [patent_app_date] => 2001-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4716 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754684.pdf [firstpage_image] =>[orig_patent_app_number] => 09853874 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1183127 [patent_doc_number] => 06751638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-15 [patent_title] => 'Min and max operations for multiplication and/or division under the simple interval system' [patent_app_type] => B2 [patent_app_number] => 09/854096 [patent_app_country] => US [patent_app_date] => 2001-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5058 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751638.pdf [firstpage_image] =>[orig_patent_app_number] => 09854096 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1169208 [patent_doc_number] => 06766344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'Processing Galois Field arithmetic' [patent_app_type] => B2 [patent_app_number] => 09/851236 [patent_app_country] => US [patent_app_date] => 2001-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7970 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766344.pdf [firstpage_image] =>[orig_patent_app_number] => 09851236 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5890196 [patent_doc_number] => 20020013799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Accelerated montgomery multiplication using plural multipliers' [patent_app_type] => new [patent_app_number] => 09/849667 [patent_app_country] => US [patent_app_date] => 2001-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7797 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20020013799.pdf [firstpage_image] =>[orig_patent_app_number] => 09849667 [rel_patent_id] =>[rel_patent_doc_number] =>)