Search

Tan V. Mai

Examiner (ID: 15743)

Most Active Art Unit
2193
Art Unit(s)
2306, 2193, 2787, 2786, 2121, 2124, 2302, 2301, 2182, 2183
Total Applications
3863
Issued Applications
3431
Pending Applications
94
Abandoned Applications
349

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 658994 [patent_doc_number] => 07111030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-19 [patent_title] => 'Method of detecting pilot tones in a noisy signal' [patent_app_type] => utility [patent_app_number] => 10/450515 [patent_app_country] => US [patent_app_date] => 2000-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3178 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/111/07111030.pdf [firstpage_image] =>[orig_patent_app_number] => 10450515 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/450515
Method of detecting pilot tones in a noisy signal Dec 19, 2000 Issued
Array ( [id] => 1168802 [patent_doc_number] => 06763365 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-13 [patent_title] => 'Hardware implementation for modular multiplication using a plurality of almost entirely identical processor elements' [patent_app_type] => B2 [patent_app_number] => 09/740685 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 30 [patent_no_of_words] => 22582 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/763/06763365.pdf [firstpage_image] =>[orig_patent_app_number] => 09740685 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/740685
Hardware implementation for modular multiplication using a plurality of almost entirely identical processor elements Dec 18, 2000 Issued
Array ( [id] => 1233839 [patent_doc_number] => 06697830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-24 [patent_title] => 'Polynomial coefficient generator' [patent_app_type] => B2 [patent_app_number] => 09/740447 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3008 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697830.pdf [firstpage_image] =>[orig_patent_app_number] => 09740447 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/740447
Polynomial coefficient generator Dec 18, 2000 Issued
Array ( [id] => 1116456 [patent_doc_number] => 06804696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-12 [patent_title] => 'Pipelining operations in a system for performing modular multiplication' [patent_app_type] => B2 [patent_app_number] => 09/740485 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 30 [patent_no_of_words] => 22494 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/804/06804696.pdf [firstpage_image] =>[orig_patent_app_number] => 09740485 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/740485
Pipelining operations in a system for performing modular multiplication Dec 18, 2000 Issued
Array ( [id] => 744530 [patent_doc_number] => 07035892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-25 [patent_title] => 'Apparatus and method for reducing precision of data' [patent_app_type] => utility [patent_app_number] => 09/735170 [patent_app_country] => US [patent_app_date] => 2000-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11554 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/035/07035892.pdf [firstpage_image] =>[orig_patent_app_number] => 09735170 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735170
Apparatus and method for reducing precision of data Dec 10, 2000 Issued
Array ( [id] => 619090 [patent_doc_number] => 07146396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-05 [patent_title] => 'Method and apparatus of convolving signals' [patent_app_type] => utility [patent_app_number] => 10/149470 [patent_app_country] => US [patent_app_date] => 2000-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4254 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/146/07146396.pdf [firstpage_image] =>[orig_patent_app_number] => 10149470 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/149470
Method and apparatus of convolving signals Dec 9, 2000 Issued
Array ( [id] => 1169228 [patent_doc_number] => 06766346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'System and method for computing a square of a number' [patent_app_type] => B2 [patent_app_number] => 09/725927 [patent_app_country] => US [patent_app_date] => 2000-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 3869 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766346.pdf [firstpage_image] =>[orig_patent_app_number] => 09725927 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/725927
System and method for computing a square of a number Nov 29, 2000 Issued
Array ( [id] => 6310118 [patent_doc_number] => 20020095450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Method and device for computing the number of bits set to one in an arbitrary length word' [patent_app_type] => new [patent_app_number] => 09/727135 [patent_app_country] => US [patent_app_date] => 2000-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3235 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20020095450.pdf [firstpage_image] =>[orig_patent_app_number] => 09727135 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/727135
Method and device for computing the number of bits set to one in an arbitrary length word Nov 29, 2000 Issued
Array ( [id] => 1116452 [patent_doc_number] => 06804695 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-12 [patent_title] => 'Method and apparatus for constraining tap coefficients in an adaptive finite impulse response filter' [patent_app_type] => B1 [patent_app_number] => 09/717240 [patent_app_country] => US [patent_app_date] => 2000-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5744 [patent_no_of_claims] => 140 [patent_no_of_ind_claims] => 62 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/804/06804695.pdf [firstpage_image] =>[orig_patent_app_number] => 09717240 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/717240
Method and apparatus for constraining tap coefficients in an adaptive finite impulse response filter Nov 21, 2000 Issued
Array ( [id] => 1186201 [patent_doc_number] => 06742007 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-25 [patent_title] => 'Programmable digital arithmetic circuit, device using programmable digital arithmetic circuit and method for making a programmable digital arithmetic circuit' [patent_app_type] => B1 [patent_app_number] => 09/716290 [patent_app_country] => US [patent_app_date] => 2000-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 4642 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/742/06742007.pdf [firstpage_image] =>[orig_patent_app_number] => 09716290 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/716290
Programmable digital arithmetic circuit, device using programmable digital arithmetic circuit and method for making a programmable digital arithmetic circuit Nov 20, 2000 Issued
Array ( [id] => 1184348 [patent_doc_number] => 06748411 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-08 [patent_title] => 'Hierarchical carry-select multiple-input split adder' [patent_app_type] => B1 [patent_app_number] => 09/716474 [patent_app_country] => US [patent_app_date] => 2000-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3240 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/748/06748411.pdf [firstpage_image] =>[orig_patent_app_number] => 09716474 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/716474
Hierarchical carry-select multiple-input split adder Nov 19, 2000 Issued
Array ( [id] => 1356248 [patent_doc_number] => 06591285 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Running-sum adder networks determined by recursive construction of multi-stage networks' [patent_app_type] => B1 [patent_app_number] => 09/716574 [patent_app_country] => US [patent_app_date] => 2000-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 4235 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591285.pdf [firstpage_image] =>[orig_patent_app_number] => 09716574 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/716574
Running-sum adder networks determined by recursive construction of multi-stage networks Nov 19, 2000 Issued
Array ( [id] => 1169143 [patent_doc_number] => 06766338 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-20 [patent_title] => 'High order lagrange sample rate conversion using tables for improved efficiency' [patent_app_type] => B1 [patent_app_number] => 09/713419 [patent_app_country] => US [patent_app_date] => 2000-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3944 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766338.pdf [firstpage_image] =>[orig_patent_app_number] => 09713419 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/713419
High order lagrange sample rate conversion using tables for improved efficiency Nov 14, 2000 Issued
Array ( [id] => 7631642 [patent_doc_number] => 06665695 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Delayed adaptive least-mean-square digital filter' [patent_app_type] => B1 [patent_app_number] => 09/713417 [patent_app_country] => US [patent_app_date] => 2000-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5345 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665695.pdf [firstpage_image] =>[orig_patent_app_number] => 09713417 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/713417
Delayed adaptive least-mean-square digital filter Nov 14, 2000 Issued
Array ( [id] => 1260285 [patent_doc_number] => 06668268 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-23 [patent_title] => 'Method and apparatus for compiling dependent subtraction operations on arithmetic intervals' [patent_app_type] => B1 [patent_app_number] => 09/711095 [patent_app_country] => US [patent_app_date] => 2000-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4261 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/668/06668268.pdf [firstpage_image] =>[orig_patent_app_number] => 09711095 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/711095
Method and apparatus for compiling dependent subtraction operations on arithmetic intervals Nov 8, 2000 Issued
Array ( [id] => 1308049 [patent_doc_number] => 06629120 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Method and apparatus for performing a mask-driven interval multiplication operation' [patent_app_type] => B1 [patent_app_number] => 09/710454 [patent_app_country] => US [patent_app_date] => 2000-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5355 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629120.pdf [firstpage_image] =>[orig_patent_app_number] => 09710454 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/710454
Method and apparatus for performing a mask-driven interval multiplication operation Nov 8, 2000 Issued
09/647467 METHOD OF INTERPOLATING DATA ON TIME-SERIES SIGNAL AND RECORDING MEDIUM ON WHICH A PROGRAM THEREFOR IS RECORDED Nov 5, 2000 Abandoned
Array ( [id] => 1248696 [patent_doc_number] => 06678710 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Logarithmic number system for performing calculations in a processor' [patent_app_type] => B1 [patent_app_number] => 09/706467 [patent_app_country] => US [patent_app_date] => 2000-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 9419 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678710.pdf [firstpage_image] =>[orig_patent_app_number] => 09706467 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/706467
Logarithmic number system for performing calculations in a processor Nov 2, 2000 Issued
Array ( [id] => 712985 [patent_doc_number] => 07062526 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-13 [patent_title] => 'Microprocessor with rounding multiply instructions' [patent_app_type] => utility [patent_app_number] => 09/703140 [patent_app_country] => US [patent_app_date] => 2000-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 10102 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/062/07062526.pdf [firstpage_image] =>[orig_patent_app_number] => 09703140 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/703140
Microprocessor with rounding multiply instructions Oct 30, 2000 Issued
Array ( [id] => 1039875 [patent_doc_number] => 06874006 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-29 [patent_title] => 'Apparatus and method for rectangular-to-polar conversion' [patent_app_type] => utility [patent_app_number] => 09/698249 [patent_app_country] => US [patent_app_date] => 2000-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 102 [patent_no_of_words] => 44692 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/874/06874006.pdf [firstpage_image] =>[orig_patent_app_number] => 09698249 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/698249
Apparatus and method for rectangular-to-polar conversion Oct 29, 2000 Issued
Menu