Search

Tan V. Mai

Examiner (ID: 15743)

Most Active Art Unit
2193
Art Unit(s)
2306, 2193, 2787, 2786, 2121, 2124, 2302, 2301, 2182, 2183
Total Applications
3863
Issued Applications
3431
Pending Applications
94
Abandoned Applications
349

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1432331 [patent_doc_number] => 06505223 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Watermark detection' [patent_app_type] => B1 [patent_app_number] => 09/423277 [patent_app_country] => US [patent_app_date] => 1999-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3153 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505223.pdf [firstpage_image] =>[orig_patent_app_number] => 09423277 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/423277
Watermark detection Nov 3, 1999 Issued
Array ( [id] => 1428625 [patent_doc_number] => 06529925 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Method for reducing the crest factor of a signal' [patent_app_type] => B1 [patent_app_number] => 09/433384 [patent_app_country] => US [patent_app_date] => 1999-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3375 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529925.pdf [firstpage_image] =>[orig_patent_app_number] => 09433384 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/433384
Method for reducing the crest factor of a signal Nov 2, 1999 Issued
Array ( [id] => 1456479 [patent_doc_number] => 06457034 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method and apparatus for accumulation buffering in the video graphics system' [patent_app_type] => B1 [patent_app_number] => 09/432856 [patent_app_country] => US [patent_app_date] => 1999-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5493 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457034.pdf [firstpage_image] =>[orig_patent_app_number] => 09432856 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/432856
Method and apparatus for accumulation buffering in the video graphics system Nov 1, 1999 Issued
Array ( [id] => 690377 [patent_doc_number] => 07080108 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-07-18 [patent_title] => 'Discrete filter having a tap selection circuit' [patent_app_type] => utility [patent_app_number] => 09/432337 [patent_app_country] => US [patent_app_date] => 1999-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2644 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/080/07080108.pdf [firstpage_image] =>[orig_patent_app_number] => 09432337 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/432337
Discrete filter having a tap selection circuit Nov 1, 1999 Issued
Array ( [id] => 4387282 [patent_doc_number] => 06275842 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Low power multiplier for CPU and DSP' [patent_app_type] => 1 [patent_app_number] => 9/431851 [patent_app_country] => US [patent_app_date] => 1999-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2086 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275842.pdf [firstpage_image] =>[orig_patent_app_number] => 431851 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/431851
Low power multiplier for CPU and DSP Nov 1, 1999 Issued
Array ( [id] => 517482 [patent_doc_number] => 07203717 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-04-10 [patent_title] => 'Fast modified discrete cosine transform method' [patent_app_type] => utility [patent_app_number] => 10/129046 [patent_app_country] => US [patent_app_date] => 1999-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2955 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/203/07203717.pdf [firstpage_image] =>[orig_patent_app_number] => 10129046 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/129046
Fast modified discrete cosine transform method Oct 29, 1999 Issued
Array ( [id] => 1430987 [patent_doc_number] => 06523052 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Method and architecture to facilitate achieving a fast EPR4 equalization start-up in a magnetic recording read channel' [patent_app_type] => B1 [patent_app_number] => 09/430385 [patent_app_country] => US [patent_app_date] => 1999-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3402 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/523/06523052.pdf [firstpage_image] =>[orig_patent_app_number] => 09430385 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/430385
Method and architecture to facilitate achieving a fast EPR4 equalization start-up in a magnetic recording read channel Oct 28, 1999 Issued
Array ( [id] => 1566906 [patent_doc_number] => 06438571 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Adder circuit' [patent_app_type] => B1 [patent_app_number] => 09/428537 [patent_app_country] => US [patent_app_date] => 1999-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6125 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438571.pdf [firstpage_image] =>[orig_patent_app_number] => 09428537 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/428537
Adder circuit Oct 27, 1999 Issued
09/428607 MODULAR ARITHMETIC COPROCESSOR COMPRISING TWO MULTIPLICATION CIRCUITS WORKING IN PARALLEL Oct 26, 1999 Abandoned
Array ( [id] => 1414703 [patent_doc_number] => 06549926 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'SRT divider having several bits of each partial remainder one-hot encoded to minimize the logic levels needed to estimate quotient bits' [patent_app_type] => B1 [patent_app_number] => 09/427366 [patent_app_country] => US [patent_app_date] => 1999-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5692 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549926.pdf [firstpage_image] =>[orig_patent_app_number] => 09427366 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/427366
SRT divider having several bits of each partial remainder one-hot encoded to minimize the logic levels needed to estimate quotient bits Oct 25, 1999 Issued
Array ( [id] => 1557067 [patent_doc_number] => 06349318 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Arithmetic processor for finite field and module integer arithmetic operations' [patent_app_type] => B1 [patent_app_number] => 09/418217 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5855 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/349/06349318.pdf [firstpage_image] =>[orig_patent_app_number] => 09418217 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/418217
Arithmetic processor for finite field and module integer arithmetic operations Oct 13, 1999 Issued
Array ( [id] => 1408370 [patent_doc_number] => 06557020 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Information processing system, enciphering/deciphering system, system LSI, and electronic apparatus' [patent_app_type] => B1 [patent_app_number] => 09/367234 [patent_app_country] => US [patent_app_date] => 1999-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 19304 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557020.pdf [firstpage_image] =>[orig_patent_app_number] => 09367234 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/367234
Information processing system, enciphering/deciphering system, system LSI, and electronic apparatus Oct 12, 1999 Issued
Array ( [id] => 1308055 [patent_doc_number] => 06629121 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Surface acoustic wave-matched filter and differential detector for demodulating spread spectrum signals' [patent_app_type] => B1 [patent_app_number] => 09/413946 [patent_app_country] => US [patent_app_date] => 1999-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4407 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629121.pdf [firstpage_image] =>[orig_patent_app_number] => 09413946 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/413946
Surface acoustic wave-matched filter and differential detector for demodulating spread spectrum signals Oct 6, 1999 Issued
Array ( [id] => 4278839 [patent_doc_number] => 06205462 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Digital multiply-accumulate circuit that can operate on both integer and floating point numbers simultaneously' [patent_app_type] => 1 [patent_app_number] => 9/414322 [patent_app_country] => US [patent_app_date] => 1999-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2283 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205462.pdf [firstpage_image] =>[orig_patent_app_number] => 414322 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/414322
Digital multiply-accumulate circuit that can operate on both integer and floating point numbers simultaneously Oct 5, 1999 Issued
Array ( [id] => 1430005 [patent_doc_number] => 06526430 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Reconfigurable SIMD coprocessor architecture for sum of absolute differences and symmetric filtering (scalable MAC engine for image processing)' [patent_app_type] => B1 [patent_app_number] => 09/411124 [patent_app_country] => US [patent_app_date] => 1999-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 30 [patent_no_of_words] => 13905 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/526/06526430.pdf [firstpage_image] =>[orig_patent_app_number] => 09411124 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/411124
Reconfigurable SIMD coprocessor architecture for sum of absolute differences and symmetric filtering (scalable MAC engine for image processing) Oct 3, 1999 Issued
Array ( [id] => 6722170 [patent_doc_number] => 20030055860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'ROUNDING MECHANISMS IN PROCESSORS' [patent_app_type] => new [patent_app_number] => 09/411186 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12905 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20030055860.pdf [firstpage_image] =>[orig_patent_app_number] => 09411186 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/411186
Rounding mechanisms in processors Sep 30, 1999 Issued
Array ( [id] => 1384941 [patent_doc_number] => 06571268 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Multiplier accumulator circuits' [patent_app_type] => B1 [patent_app_number] => 09/411167 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 43 [patent_no_of_words] => 19677 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571268.pdf [firstpage_image] =>[orig_patent_app_number] => 09411167 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/411167
Multiplier accumulator circuits Sep 30, 1999 Issued
Array ( [id] => 1505776 [patent_doc_number] => 06487576 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Zero anticipation method and apparatus' [patent_app_type] => B1 [patent_app_number] => 09/411466 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 9839 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487576.pdf [firstpage_image] =>[orig_patent_app_number] => 09411466 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/411466
Zero anticipation method and apparatus Sep 30, 1999 Issued
Array ( [id] => 1513202 [patent_doc_number] => RE037953 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Filter circuit for communication' [patent_app_type] => E1 [patent_app_number] => 09/404783 [patent_app_country] => US [patent_app_date] => 1999-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 5015 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/037/RE037953.pdf [firstpage_image] =>[orig_patent_app_number] => 09404783 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/404783
Filter circuit for communication Sep 23, 1999 Issued
Array ( [id] => 7645968 [patent_doc_number] => 06477554 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Circuit and method for computing a fast fourier transform' [patent_app_type] => B1 [patent_app_number] => 09/398636 [patent_app_country] => US [patent_app_date] => 1999-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5521 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477554.pdf [firstpage_image] =>[orig_patent_app_number] => 09398636 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/398636
Circuit and method for computing a fast fourier transform Sep 16, 1999 Issued
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