Search

Tan V. Mai

Examiner (ID: 15743)

Most Active Art Unit
2193
Art Unit(s)
2306, 2193, 2787, 2786, 2121, 2124, 2302, 2301, 2182, 2183
Total Applications
3863
Issued Applications
3431
Pending Applications
94
Abandoned Applications
349

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1405591 [patent_doc_number] => 06560623 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method and apparatus for producing correctly rounded values of functions using double precision operands' [patent_app_type] => B1 [patent_app_number] => 09/397267 [patent_app_country] => US [patent_app_date] => 1999-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 12779 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560623.pdf [firstpage_image] =>[orig_patent_app_number] => 09397267 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/397267
Method and apparatus for producing correctly rounded values of functions using double precision operands Sep 15, 1999 Issued
Array ( [id] => 1552508 [patent_doc_number] => 06446104 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Double precision floating point multiplier having a 32-bit booth-encoded array multiplier' [patent_app_type] => B1 [patent_app_number] => 09/396236 [patent_app_country] => US [patent_app_date] => 1999-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5930 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446104.pdf [firstpage_image] =>[orig_patent_app_number] => 09396236 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/396236
Double precision floating point multiplier having a 32-bit booth-encoded array multiplier Sep 14, 1999 Issued
Array ( [id] => 1416380 [patent_doc_number] => 06532485 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Method and apparatus for performing multiplication/addition operations' [patent_app_type] => B1 [patent_app_number] => 09/391166 [patent_app_country] => US [patent_app_date] => 1999-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2432 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/532/06532485.pdf [firstpage_image] =>[orig_patent_app_number] => 09391166 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/391166
Method and apparatus for performing multiplication/addition operations Sep 7, 1999 Issued
Array ( [id] => 1508792 [patent_doc_number] => 06466957 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Reduced computation system for wavelet transforms' [patent_app_type] => B1 [patent_app_number] => 09/388754 [patent_app_country] => US [patent_app_date] => 1999-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3292 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/466/06466957.pdf [firstpage_image] =>[orig_patent_app_number] => 09388754 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/388754
Reduced computation system for wavelet transforms Sep 1, 1999 Issued
Array ( [id] => 1356227 [patent_doc_number] => 06591283 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Efficient interpolator for high speed timing recovery' [patent_app_type] => B1 [patent_app_number] => 09/387104 [patent_app_country] => US [patent_app_date] => 1999-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 5051 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591283.pdf [firstpage_image] =>[orig_patent_app_number] => 09387104 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/387104
Efficient interpolator for high speed timing recovery Aug 30, 1999 Issued
Array ( [id] => 1465873 [patent_doc_number] => 06393454 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Booth multiplier with low power, high performance input circuitry' [patent_app_type] => B1 [patent_app_number] => 09/387636 [patent_app_country] => US [patent_app_date] => 1999-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4966 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393454.pdf [firstpage_image] =>[orig_patent_app_number] => 09387636 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/387636
Booth multiplier with low power, high performance input circuitry Aug 30, 1999 Issued
Array ( [id] => 1225116 [patent_doc_number] => 06704762 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Multiplier and arithmetic unit for calculating sum of product' [patent_app_type] => B1 [patent_app_number] => 09/385357 [patent_app_country] => US [patent_app_date] => 1999-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 17229 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704762.pdf [firstpage_image] =>[orig_patent_app_number] => 09385357 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/385357
Multiplier and arithmetic unit for calculating sum of product Aug 29, 1999 Issued
Array ( [id] => 1423006 [patent_doc_number] => 06539412 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Discrete wavelet transform apparatus for lattice structure' [patent_app_type] => B1 [patent_app_number] => 09/384287 [patent_app_country] => US [patent_app_date] => 1999-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 5873 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539412.pdf [firstpage_image] =>[orig_patent_app_number] => 09384287 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/384287
Discrete wavelet transform apparatus for lattice structure Aug 26, 1999 Issued
Array ( [id] => 1250766 [patent_doc_number] => RE038374 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Training a recursive filter by use of derivative function' [patent_app_type] => E1 [patent_app_number] => 09/384047 [patent_app_country] => US [patent_app_date] => 1999-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4247 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/038/RE038374.pdf [firstpage_image] =>[orig_patent_app_number] => 09384047 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/384047
Training a recursive filter by use of derivative function Aug 25, 1999 Issued
Array ( [id] => 1465856 [patent_doc_number] => 06393450 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Switched bandwidth digital filters with slewing' [patent_app_type] => B1 [patent_app_number] => 09/382727 [patent_app_country] => US [patent_app_date] => 1999-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3437 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393450.pdf [firstpage_image] =>[orig_patent_app_number] => 09382727 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/382727
Switched bandwidth digital filters with slewing Aug 24, 1999 Issued
Array ( [id] => 1430981 [patent_doc_number] => 06523050 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Integer to floating point conversion using one\'s complement with subsequent correction to eliminate two\'s complement in critical path' [patent_app_type] => B1 [patent_app_number] => 09/377136 [patent_app_country] => US [patent_app_date] => 1999-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7991 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/523/06523050.pdf [firstpage_image] =>[orig_patent_app_number] => 09377136 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/377136
Integer to floating point conversion using one's complement with subsequent correction to eliminate two's complement in critical path Aug 18, 1999 Issued
Array ( [id] => 1384801 [patent_doc_number] => 06571263 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Random number generating apparatus' [patent_app_type] => B1 [patent_app_number] => 09/377041 [patent_app_country] => US [patent_app_date] => 1999-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2371 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571263.pdf [firstpage_image] =>[orig_patent_app_number] => 09377041 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/377041
Random number generating apparatus Aug 18, 1999 Issued
Array ( [id] => 1431204 [patent_doc_number] => 06519622 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Designing addition circuits' [patent_app_type] => B1 [patent_app_number] => 09/375317 [patent_app_country] => US [patent_app_date] => 1999-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 5232 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519622.pdf [firstpage_image] =>[orig_patent_app_number] => 09375317 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/375317
Designing addition circuits Aug 15, 1999 Issued
Array ( [id] => 4291243 [patent_doc_number] => 06247034 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Fast fourier transforming apparatus and method, variable bit reverse circuit, inverse fast fourier transforming apparatus and method, and OFDM receiver and transmitter' [patent_app_type] => 1 [patent_app_number] => 9/371923 [patent_app_country] => US [patent_app_date] => 1999-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 40 [patent_no_of_words] => 15750 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247034.pdf [firstpage_image] =>[orig_patent_app_number] => 371923 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/371923
Fast fourier transforming apparatus and method, variable bit reverse circuit, inverse fast fourier transforming apparatus and method, and OFDM receiver and transmitter Aug 10, 1999 Issued
Array ( [id] => 1462296 [patent_doc_number] => 06427159 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'ARITHMETIC UNIT, DIGITAL SIGNAL PROCESSOR, METHOD OF SCHEDULING MULTIPLICATION IN AN ARITHMETIC UNIT, METHOD OF SELECTIVELY DELAYING ADDING AND METHOD OF SELECTIVELY ADDING DURING A FIRST OR SECOND CLOCK CYCLE' [patent_app_type] => B1 [patent_app_number] => 09/366504 [patent_app_country] => US [patent_app_date] => 1999-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3759 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/427/06427159.pdf [firstpage_image] =>[orig_patent_app_number] => 09366504 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/366504
ARITHMETIC UNIT, DIGITAL SIGNAL PROCESSOR, METHOD OF SCHEDULING MULTIPLICATION IN AN ARITHMETIC UNIT, METHOD OF SELECTIVELY DELAYING ADDING AND METHOD OF SELECTIVELY ADDING DURING A FIRST OR SECOND CLOCK CYCLE Aug 2, 1999 Issued
Array ( [id] => 4370226 [patent_doc_number] => 06216145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Overlapped reversible transforms for unified lossless/lossy compression' [patent_app_type] => 1 [patent_app_number] => 9/364856 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 52 [patent_no_of_words] => 19706 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/216/06216145.pdf [firstpage_image] =>[orig_patent_app_number] => 364856 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364856
Overlapped reversible transforms for unified lossless/lossy compression Jul 29, 1999 Issued
Array ( [id] => 1484705 [patent_doc_number] => 06453331 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Method and system for filtering force constant table for accurate torque modeling' [patent_app_type] => B1 [patent_app_number] => 09/364465 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4045 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453331.pdf [firstpage_image] =>[orig_patent_app_number] => 09364465 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364465
Method and system for filtering force constant table for accurate torque modeling Jul 29, 1999 Issued
Array ( [id] => 1233847 [patent_doc_number] => 06697832 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-24 [patent_title] => 'Floating-point processor with improved intermediate result handling' [patent_app_type] => B1 [patent_app_number] => 09/364514 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6343 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697832.pdf [firstpage_image] =>[orig_patent_app_number] => 09364514 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364514
Floating-point processor with improved intermediate result handling Jul 29, 1999 Issued
Array ( [id] => 1001541 [patent_doc_number] => 06912559 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-28 [patent_title] => 'System and method for improving the accuracy of reciprocal square root operations performed by a floating-point unit' [patent_app_type] => utility [patent_app_number] => 09/363637 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5241 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/912/06912559.pdf [firstpage_image] =>[orig_patent_app_number] => 09363637 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/363637
System and method for improving the accuracy of reciprocal square root operations performed by a floating-point unit Jul 29, 1999 Issued
Array ( [id] => 4401405 [patent_doc_number] => 06279023 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'System for computing the multiplicative inverse of an element of a Galois field without using tables' [patent_app_type] => 1 [patent_app_number] => 9/363611 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5782 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279023.pdf [firstpage_image] =>[orig_patent_app_number] => 363611 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/363611
System for computing the multiplicative inverse of an element of a Galois field without using tables Jul 28, 1999 Issued
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