Search

Tan V. Mai

Examiner (ID: 15743)

Most Active Art Unit
2193
Art Unit(s)
2306, 2193, 2787, 2786, 2121, 2124, 2302, 2301, 2182, 2183
Total Applications
3863
Issued Applications
3431
Pending Applications
94
Abandoned Applications
349

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1294582 [patent_doc_number] => 06640237 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-28 [patent_title] => 'Method and system for generating a trigonometric function' [patent_app_type] => B1 [patent_app_number] => 09/361917 [patent_app_country] => US [patent_app_date] => 1999-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5182 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/640/06640237.pdf [firstpage_image] =>[orig_patent_app_number] => 09361917 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/361917
Method and system for generating a trigonometric function Jul 26, 1999 Issued
Array ( [id] => 4316493 [patent_doc_number] => 06182103 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Finite impluse response bandpass filter' [patent_app_type] => 1 [patent_app_number] => 9/360547 [patent_app_country] => US [patent_app_date] => 1999-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5136 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/182/06182103.pdf [firstpage_image] =>[orig_patent_app_number] => 360547 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/360547
Finite impluse response bandpass filter Jul 25, 1999 Issued
Array ( [id] => 1480646 [patent_doc_number] => 06389445 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Methods and systems for designing and making signal-processor circuits with internal companding, and the resulting circuits' [patent_app_type] => B1 [patent_app_number] => 09/358293 [patent_app_country] => US [patent_app_date] => 1999-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 2889 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389445.pdf [firstpage_image] =>[orig_patent_app_number] => 09358293 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/358293
Methods and systems for designing and making signal-processor circuits with internal companding, and the resulting circuits Jul 20, 1999 Issued
Array ( [id] => 1538758 [patent_doc_number] => 06411977 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Method for reducing computational errors in a useful band of a signal generated with a fourier transform, for fixed-point microprocessors' [patent_app_type] => B1 [patent_app_number] => 09/356554 [patent_app_country] => US [patent_app_date] => 1999-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1312 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/411/06411977.pdf [firstpage_image] =>[orig_patent_app_number] => 09356554 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/356554
Method for reducing computational errors in a useful band of a signal generated with a fourier transform, for fixed-point microprocessors Jul 18, 1999 Issued
Array ( [id] => 1512984 [patent_doc_number] => 06442580 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Resampling method and resampler circuit' [patent_app_type] => B1 [patent_app_number] => 09/357157 [patent_app_country] => US [patent_app_date] => 1999-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9253 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442580.pdf [firstpage_image] =>[orig_patent_app_number] => 09357157 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/357157
Resampling method and resampler circuit Jul 18, 1999 Issued
Array ( [id] => 7642459 [patent_doc_number] => 06430587 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Method and apparatus for FFT computation' [patent_app_type] => B1 [patent_app_number] => 09/353876 [patent_app_country] => US [patent_app_date] => 1999-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3368 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430587.pdf [firstpage_image] =>[orig_patent_app_number] => 09353876 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/353876
Method and apparatus for FFT computation Jul 14, 1999 Issued
Array ( [id] => 1480622 [patent_doc_number] => 06389439 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Random-number generating method and apparatus and storage medium therefor' [patent_app_type] => B1 [patent_app_number] => 09/353146 [patent_app_country] => US [patent_app_date] => 1999-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5552 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389439.pdf [firstpage_image] =>[orig_patent_app_number] => 09353146 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/353146
Random-number generating method and apparatus and storage medium therefor Jul 13, 1999 Issued
Array ( [id] => 1452034 [patent_doc_number] => 06370559 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Method and apparatus for performing N bit by 2*N1 bit signed multiplications' [patent_app_type] => B1 [patent_app_number] => 09/354004 [patent_app_country] => US [patent_app_date] => 1999-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8755 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370559.pdf [firstpage_image] =>[orig_patent_app_number] => 09354004 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/354004
Method and apparatus for performing N bit by 2*N1 bit signed multiplications Jul 12, 1999 Issued
Array ( [id] => 1578532 [patent_doc_number] => 06469988 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Low-level circuit implementation of signal flow graphs for real-time signal processing of high-speed digital signals' [patent_app_type] => B1 [patent_app_number] => 09/349832 [patent_app_country] => US [patent_app_date] => 1999-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3379 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/469/06469988.pdf [firstpage_image] =>[orig_patent_app_number] => 09349832 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/349832
Low-level circuit implementation of signal flow graphs for real-time signal processing of high-speed digital signals Jul 7, 1999 Issued
Array ( [id] => 1313862 [patent_doc_number] => 06622153 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'Virtual parallel multiplier-accumulator' [patent_app_type] => B1 [patent_app_number] => 09/348447 [patent_app_country] => US [patent_app_date] => 1999-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5563 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/622/06622153.pdf [firstpage_image] =>[orig_patent_app_number] => 09348447 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/348447
Virtual parallel multiplier-accumulator Jul 6, 1999 Issued
Array ( [id] => 1501335 [patent_doc_number] => 06405233 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Unaligned semaphore adder' [patent_app_type] => B1 [patent_app_number] => 09/345717 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7201 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405233.pdf [firstpage_image] =>[orig_patent_app_number] => 09345717 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/345717
Unaligned semaphore adder Jun 29, 1999 Issued
Array ( [id] => 1524725 [patent_doc_number] => 06415311 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Sign extension circuit and method for unsigned multiplication and accumulation' [patent_app_type] => B1 [patent_app_number] => 09/344175 [patent_app_country] => US [patent_app_date] => 1999-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2098 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415311.pdf [firstpage_image] =>[orig_patent_app_number] => 09344175 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/344175
Sign extension circuit and method for unsigned multiplication and accumulation Jun 23, 1999 Issued
Array ( [id] => 1416366 [patent_doc_number] => 06532484 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Parallel system and method for performing fast fourier transform' [patent_app_type] => B1 [patent_app_number] => 09/337587 [patent_app_country] => US [patent_app_date] => 1999-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3619 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/532/06532484.pdf [firstpage_image] =>[orig_patent_app_number] => 09337587 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/337587
Parallel system and method for performing fast fourier transform Jun 20, 1999 Issued
Array ( [id] => 1323553 [patent_doc_number] => 06611855 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-26 [patent_title] => 'Flexible and efficient channelizer architecture' [patent_app_type] => B1 [patent_app_number] => 09/337344 [patent_app_country] => US [patent_app_date] => 1999-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3784 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/611/06611855.pdf [firstpage_image] =>[orig_patent_app_number] => 09337344 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/337344
Flexible and efficient channelizer architecture Jun 20, 1999 Issued
Array ( [id] => 1604396 [patent_doc_number] => 06434582 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Cosine algorithm for relatively small angles' [patent_app_type] => B1 [patent_app_number] => 09/336394 [patent_app_country] => US [patent_app_date] => 1999-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 13042 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434582.pdf [firstpage_image] =>[orig_patent_app_number] => 09336394 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/336394
Cosine algorithm for relatively small angles Jun 17, 1999 Issued
Array ( [id] => 1552513 [patent_doc_number] => 06446105 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Method and medium for operating a vector computer' [patent_app_type] => B1 [patent_app_number] => 09/335705 [patent_app_country] => US [patent_app_date] => 1999-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 5006 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446105.pdf [firstpage_image] =>[orig_patent_app_number] => 09335705 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/335705
Method and medium for operating a vector computer Jun 17, 1999 Issued
Array ( [id] => 1595668 [patent_doc_number] => 06484194 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Low cost multiplier block with chain capability' [patent_app_type] => B1 [patent_app_number] => 09/334995 [patent_app_country] => US [patent_app_date] => 1999-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8431 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/484/06484194.pdf [firstpage_image] =>[orig_patent_app_number] => 09334995 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/334995
Low cost multiplier block with chain capability Jun 16, 1999 Issued
Array ( [id] => 1604398 [patent_doc_number] => 06434584 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Flexible accumulator register file for use in high performance microprocessors' [patent_app_type] => B1 [patent_app_number] => 09/335356 [patent_app_country] => US [patent_app_date] => 1999-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13590 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434584.pdf [firstpage_image] =>[orig_patent_app_number] => 09335356 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/335356
Flexible accumulator register file for use in high performance microprocessors Jun 16, 1999 Issued
Array ( [id] => 1420540 [patent_doc_number] => 06542915 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Floating point pipeline with a leading zeros anticipator circuit' [patent_app_type] => B1 [patent_app_number] => 09/335284 [patent_app_country] => US [patent_app_date] => 1999-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4035 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542915.pdf [firstpage_image] =>[orig_patent_app_number] => 09335284 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/335284
Floating point pipeline with a leading zeros anticipator circuit Jun 16, 1999 Issued
Array ( [id] => 4203272 [patent_doc_number] => 06151617 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Multiplier circuit for multiplication operation between binary and twos complement numbers' [patent_app_type] => 1 [patent_app_number] => 9/333693 [patent_app_country] => US [patent_app_date] => 1999-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5306 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151617.pdf [firstpage_image] =>[orig_patent_app_number] => 333693 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/333693
Multiplier circuit for multiplication operation between binary and twos complement numbers Jun 15, 1999 Issued
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