Search

Tan V. Mai

Examiner (ID: 15743)

Most Active Art Unit
2193
Art Unit(s)
2306, 2193, 2787, 2786, 2121, 2124, 2302, 2301, 2182, 2183
Total Applications
3863
Issued Applications
3431
Pending Applications
94
Abandoned Applications
349

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4309102 [patent_doc_number] => 06212538 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Method for the performance of an integer division with a modular arithmetic coprocessor' [patent_app_type] => 1 [patent_app_number] => 9/143292 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 6716 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212538.pdf [firstpage_image] =>[orig_patent_app_number] => 143292 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/143292
Method for the performance of an integer division with a modular arithmetic coprocessor Aug 27, 1998 Issued
Array ( [id] => 4426488 [patent_doc_number] => 06178437 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Method and apparatus for anticipating leading digits and normalization shift amounts in a floating-point processor' [patent_app_type] => 1 [patent_app_number] => 9/139940 [patent_app_country] => US [patent_app_date] => 1998-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3241 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178437.pdf [firstpage_image] =>[orig_patent_app_number] => 139940 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/139940
Method and apparatus for anticipating leading digits and normalization shift amounts in a floating-point processor Aug 24, 1998 Issued
Array ( [id] => 4279859 [patent_doc_number] => 06260056 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Circuit and method for fast squaring by breaking the square into a plurality of terms' [patent_app_type] => 1 [patent_app_number] => 9/138301 [patent_app_country] => US [patent_app_date] => 1998-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1850 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260056.pdf [firstpage_image] =>[orig_patent_app_number] => 138301 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/138301
Circuit and method for fast squaring by breaking the square into a plurality of terms Aug 20, 1998 Issued
09/125490 DIGITAL FILTER Aug 19, 1998 Abandoned
Array ( [id] => 4191650 [patent_doc_number] => 06141672 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Tunable digital filter arrangement' [patent_app_type] => 1 [patent_app_number] => 9/136187 [patent_app_country] => US [patent_app_date] => 1998-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1588 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141672.pdf [firstpage_image] =>[orig_patent_app_number] => 136187 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/136187
Tunable digital filter arrangement Aug 18, 1998 Issued
Array ( [id] => 1571994 [patent_doc_number] => 06377967 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Efficient digital integration technique filter' [patent_app_type] => B1 [patent_app_number] => 09/132964 [patent_app_country] => US [patent_app_date] => 1998-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2388 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/377/06377967.pdf [firstpage_image] =>[orig_patent_app_number] => 09132964 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/132964
Efficient digital integration technique filter Aug 11, 1998 Issued
Array ( [id] => 4132341 [patent_doc_number] => 06047303 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Systolic architecture for computing an inverse discrete wavelet transforms' [patent_app_type] => 1 [patent_app_number] => 9/130246 [patent_app_country] => US [patent_app_date] => 1998-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8385 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/047/06047303.pdf [firstpage_image] =>[orig_patent_app_number] => 130246 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/130246
Systolic architecture for computing an inverse discrete wavelet transforms Aug 5, 1998 Issued
Array ( [id] => 4125948 [patent_doc_number] => 06058403 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Broken stack priority encoder' [patent_app_type] => 1 [patent_app_number] => 9/130379 [patent_app_country] => US [patent_app_date] => 1998-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3582 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058403.pdf [firstpage_image] =>[orig_patent_app_number] => 130379 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/130379
Broken stack priority encoder Aug 5, 1998 Issued
Array ( [id] => 4309129 [patent_doc_number] => 06212540 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Filter circuit' [patent_app_type] => 1 [patent_app_number] => 9/117528 [patent_app_country] => US [patent_app_date] => 1998-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 36 [patent_no_of_words] => 14000 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212540.pdf [firstpage_image] =>[orig_patent_app_number] => 117528 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/117528
Filter circuit Aug 2, 1998 Issued
Array ( [id] => 4191707 [patent_doc_number] => 06141676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Digitally-configurable analog VLSI chip and method for real-time solution of partial differential equations' [patent_app_type] => 1 [patent_app_number] => 9/120986 [patent_app_country] => US [patent_app_date] => 1998-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 34 [patent_no_of_words] => 8248 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141676.pdf [firstpage_image] =>[orig_patent_app_number] => 120986 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/120986
Digitally-configurable analog VLSI chip and method for real-time solution of partial differential equations Jul 21, 1998 Issued
Array ( [id] => 4203244 [patent_doc_number] => 06151615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Method and apparatus for formatting an intermediate result for parallel normalization and rounding technique for floating point arithmetic operations' [patent_app_type] => 1 [patent_app_number] => 9/120776 [patent_app_country] => US [patent_app_date] => 1998-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 9317 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151615.pdf [firstpage_image] =>[orig_patent_app_number] => 120776 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/120776
Method and apparatus for formatting an intermediate result for parallel normalization and rounding technique for floating point arithmetic operations Jul 21, 1998 Issued
Array ( [id] => 4100446 [patent_doc_number] => 06163790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Modular arithmetic coprocessor comprising an integer division circuit' [patent_app_type] => 1 [patent_app_number] => 9/101615 [patent_app_country] => US [patent_app_date] => 1998-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4447 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163790.pdf [firstpage_image] =>[orig_patent_app_number] => 101615 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/101615
Modular arithmetic coprocessor comprising an integer division circuit Jul 8, 1998 Issued
Array ( [id] => 4202917 [patent_doc_number] => 06161120 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Apparatus for performing a division operation, especially for three-dimensional graphics' [patent_app_type] => 1 [patent_app_number] => 9/110846 [patent_app_country] => US [patent_app_date] => 1998-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3244 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/161/06161120.pdf [firstpage_image] =>[orig_patent_app_number] => 110846 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/110846
Apparatus for performing a division operation, especially for three-dimensional graphics Jul 6, 1998 Issued
Array ( [id] => 4100393 [patent_doc_number] => 06163787 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Facility for reducing a data rate' [patent_app_type] => 1 [patent_app_number] => 9/110004 [patent_app_country] => US [patent_app_date] => 1998-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5229 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163787.pdf [firstpage_image] =>[orig_patent_app_number] => 110004 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/110004
Facility for reducing a data rate Jul 1, 1998 Issued
Array ( [id] => 4426485 [patent_doc_number] => 06178436 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Apparatus and method for multiplication in large finite fields' [patent_app_type] => 1 [patent_app_number] => 9/108998 [patent_app_country] => US [patent_app_date] => 1998-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 5 [patent_no_of_words] => 4879 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178436.pdf [firstpage_image] =>[orig_patent_app_number] => 108998 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/108998
Apparatus and method for multiplication in large finite fields Jun 30, 1998 Issued
Array ( [id] => 4137814 [patent_doc_number] => 06073154 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Computing multidimensional DFTs in FPGA' [patent_app_type] => 1 [patent_app_number] => 9/105072 [patent_app_country] => US [patent_app_date] => 1998-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5339 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073154.pdf [firstpage_image] =>[orig_patent_app_number] => 105072 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/105072
Computing multidimensional DFTs in FPGA Jun 25, 1998 Issued
Array ( [id] => 4373166 [patent_doc_number] => 06292814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Methods and apparatus for implementing a sign function' [patent_app_type] => 1 [patent_app_number] => 9/105225 [patent_app_country] => US [patent_app_date] => 1998-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4520 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292814.pdf [firstpage_image] =>[orig_patent_app_number] => 105225 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/105225
Methods and apparatus for implementing a sign function Jun 25, 1998 Issued
Array ( [id] => 4424187 [patent_doc_number] => 06266689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Complex switched capacitor filter and designing method for such a filter' [patent_app_type] => 1 [patent_app_number] => 9/105200 [patent_app_country] => US [patent_app_date] => 1998-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 1951 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266689.pdf [firstpage_image] =>[orig_patent_app_number] => 105200 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/105200
Complex switched capacitor filter and designing method for such a filter Jun 25, 1998 Issued
Array ( [id] => 4100409 [patent_doc_number] => 06163788 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Programmable finite impulse response processor with scalable dynamic data range' [patent_app_type] => 1 [patent_app_number] => 9/104341 [patent_app_country] => US [patent_app_date] => 1998-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3324 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163788.pdf [firstpage_image] =>[orig_patent_app_number] => 104341 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/104341
Programmable finite impulse response processor with scalable dynamic data range Jun 24, 1998 Issued
Array ( [id] => 4315454 [patent_doc_number] => 06199087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Apparatus and method for efficient arithmetic in finite fields through alternative representation' [patent_app_type] => 1 [patent_app_number] => 9/104894 [patent_app_country] => US [patent_app_date] => 1998-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4973 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/199/06199087.pdf [firstpage_image] =>[orig_patent_app_number] => 104894 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/104894
Apparatus and method for efficient arithmetic in finite fields through alternative representation Jun 24, 1998 Issued
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