
Tan V. Mai
Examiner (ID: 15743)
| Most Active Art Unit | 2193 |
| Art Unit(s) | 2306, 2193, 2787, 2786, 2121, 2124, 2302, 2301, 2182, 2183 |
| Total Applications | 3863 |
| Issued Applications | 3431 |
| Pending Applications | 94 |
| Abandoned Applications | 349 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4315508
[patent_doc_number] => 06199091
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-06
[patent_title] => 'Carry skip adder'
[patent_app_type] => 1
[patent_app_number] => 9/102532
[patent_app_country] => US
[patent_app_date] => 1998-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 15123
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/199/06199091.pdf
[firstpage_image] =>[orig_patent_app_number] => 102532
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/102532 | Carry skip adder | Jun 21, 1998 | Issued |
Array
(
[id] => 4315493
[patent_doc_number] => 06199090
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-06
[patent_title] => 'Double incrementing, low overhead, adder'
[patent_app_type] => 1
[patent_app_number] => 9/100499
[patent_app_country] => US
[patent_app_date] => 1998-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 4149
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/199/06199090.pdf
[firstpage_image] =>[orig_patent_app_number] => 100499
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/100499 | Double incrementing, low overhead, adder | Jun 18, 1998 | Issued |
Array
(
[id] => 4137843
[patent_doc_number] => 06073156
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-06
[patent_title] => 'Circuit and method for wrap-around sign extension for signed numbers using replacement of most significant bit'
[patent_app_type] => 1
[patent_app_number] => 9/100446
[patent_app_country] => US
[patent_app_date] => 1998-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 3837
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/073/06073156.pdf
[firstpage_image] =>[orig_patent_app_number] => 100446
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/100446 | Circuit and method for wrap-around sign extension for signed numbers using replacement of most significant bit | Jun 18, 1998 | Issued |
Array
(
[id] => 7642457
[patent_doc_number] => 06430589
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-06
[patent_title] => 'Single precision array processor'
[patent_app_type] => B1
[patent_app_number] => 09/100448
[patent_app_country] => US
[patent_app_date] => 1998-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 11514
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 4
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/430/06430589.pdf
[firstpage_image] =>[orig_patent_app_number] => 09100448
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/100448 | Single precision array processor | Jun 18, 1998 | Issued |
Array
(
[id] => 4315393
[patent_doc_number] => 06199083
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-06
[patent_title] => 'Computer implemented method for interpolating a value corresponding to a point represented by binary coordinates'
[patent_app_type] => 1
[patent_app_number] => 9/100640
[patent_app_country] => US
[patent_app_date] => 1998-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3351
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 14
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/199/06199083.pdf
[firstpage_image] =>[orig_patent_app_number] => 100640
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/100640 | Computer implemented method for interpolating a value corresponding to a point represented by binary coordinates | Jun 18, 1998 | Issued |
Array
(
[id] => 4336358
[patent_doc_number] => 06249799
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-19
[patent_title] => 'Selective carry boundary'
[patent_app_type] => 1
[patent_app_number] => 9/099850
[patent_app_country] => US
[patent_app_date] => 1998-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3772
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/249/06249799.pdf
[firstpage_image] =>[orig_patent_app_number] => 099850
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/099850 | Selective carry boundary | Jun 18, 1998 | Issued |
Array
(
[id] => 4351034
[patent_doc_number] => 06314444
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-06
[patent_title] => 'Second order filter-delay element for generalized analog transversal equalizer'
[patent_app_type] => 1
[patent_app_number] => 9/099724
[patent_app_country] => US
[patent_app_date] => 1998-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 5221
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/314/06314444.pdf
[firstpage_image] =>[orig_patent_app_number] => 099724
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/099724 | Second order filter-delay element for generalized analog transversal equalizer | Jun 18, 1998 | Issued |
Array
(
[id] => 4259230
[patent_doc_number] => 06167422
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-26
[patent_title] => 'Booth multiplication structure which selectively integrates the function of either of incrementing or negating with the function of booth multiplication'
[patent_app_type] => 1
[patent_app_number] => 9/099575
[patent_app_country] => US
[patent_app_date] => 1998-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 3050
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/167/06167422.pdf
[firstpage_image] =>[orig_patent_app_number] => 099575
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/099575 | Booth multiplication structure which selectively integrates the function of either of incrementing or negating with the function of booth multiplication | Jun 18, 1998 | Issued |
Array
(
[id] => 4365310
[patent_doc_number] => 06286023
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-04
[patent_title] => 'Partitioned adder tree supported by a multiplexer configuration'
[patent_app_type] => 1
[patent_app_number] => 9/100385
[patent_app_country] => US
[patent_app_date] => 1998-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3830
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/286/06286023.pdf
[firstpage_image] =>[orig_patent_app_number] => 100385
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/100385 | Partitioned adder tree supported by a multiplexer configuration | Jun 18, 1998 | Issued |
Array
(
[id] => 4256195
[patent_doc_number] => 06081823
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-27
[patent_title] => 'Circuit and method for wrap-around sign extension for signed numbers'
[patent_app_type] => 1
[patent_app_number] => 9/100266
[patent_app_country] => US
[patent_app_date] => 1998-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 3836
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/081/06081823.pdf
[firstpage_image] =>[orig_patent_app_number] => 100266
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/100266 | Circuit and method for wrap-around sign extension for signed numbers | Jun 18, 1998 | Issued |
Array
(
[id] => 4267937
[patent_doc_number] => 06138133
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-24
[patent_title] => 'Circuit for calculating the inverse of an arbitrary element of a finite field'
[patent_app_type] => 1
[patent_app_number] => 9/099275
[patent_app_country] => US
[patent_app_date] => 1998-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3334
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/138/06138133.pdf
[firstpage_image] =>[orig_patent_app_number] => 099275
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/099275 | Circuit for calculating the inverse of an arbitrary element of a finite field | Jun 17, 1998 | Issued |
Array
(
[id] => 4123060
[patent_doc_number] => 06101519
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-08
[patent_title] => 'Method for efficiently determining a fermi-dirac integrals'
[patent_app_type] => 1
[patent_app_number] => 9/098909
[patent_app_country] => US
[patent_app_date] => 1998-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2836
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/101/06101519.pdf
[firstpage_image] =>[orig_patent_app_number] => 098909
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/098909 | Method for efficiently determining a fermi-dirac integrals | Jun 16, 1998 | Issued |
Array
(
[id] => 4123103
[patent_doc_number] => 06101522
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-08
[patent_title] => 'Product-sum calculation circuit constructed of small-size ROM'
[patent_app_type] => 1
[patent_app_number] => 9/086486
[patent_app_country] => US
[patent_app_date] => 1998-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 6590
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/101/06101522.pdf
[firstpage_image] =>[orig_patent_app_number] => 086486
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/086486 | Product-sum calculation circuit constructed of small-size ROM | May 28, 1998 | Issued |
| 09/081833 | LEADER BIT ANTICIPATOR FOR FLOATING POINT MULTIPLICATION | May 18, 1998 | Abandoned |
| 09/078354 | PARALLEL DIGITAL DATA COMMUNICATIONS | May 11, 1998 | Abandoned |
Array
(
[id] => 4268000
[patent_doc_number] => 06138138
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-24
[patent_title] => 'High speed multiple determination apparatus'
[patent_app_type] => 1
[patent_app_number] => 9/073404
[patent_app_country] => US
[patent_app_date] => 1998-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6628
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/138/06138138.pdf
[firstpage_image] =>[orig_patent_app_number] => 073404
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/073404 | High speed multiple determination apparatus | May 6, 1998 | Issued |
Array
(
[id] => 4191605
[patent_doc_number] => 06141669
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-31
[patent_title] => 'Pseudorandom binary sequence block shifter'
[patent_app_type] => 1
[patent_app_number] => 9/073453
[patent_app_country] => US
[patent_app_date] => 1998-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 3347
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/141/06141669.pdf
[firstpage_image] =>[orig_patent_app_number] => 073453
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/073453 | Pseudorandom binary sequence block shifter | May 5, 1998 | Issued |
Array
(
[id] => 4254059
[patent_doc_number] => 06119141
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-12
[patent_title] => 'Resistive decoupling of function selection signals from input multiplexers in arithmetic logical units ALU'
[patent_app_type] => 1
[patent_app_number] => 9/073693
[patent_app_country] => US
[patent_app_date] => 1998-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3099
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/119/06119141.pdf
[firstpage_image] =>[orig_patent_app_number] => 073693
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/073693 | Resistive decoupling of function selection signals from input multiplexers in arithmetic logical units ALU | May 5, 1998 | Issued |
Array
(
[id] => 4151651
[patent_doc_number] => 06148316
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-14
[patent_title] => 'Floating point unit equipped also to perform integer addition as well as floating point to integer conversion'
[patent_app_type] => 1
[patent_app_number] => 9/072774
[patent_app_country] => US
[patent_app_date] => 1998-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4392
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/148/06148316.pdf
[firstpage_image] =>[orig_patent_app_number] => 072774
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/072774 | Floating point unit equipped also to perform integer addition as well as floating point to integer conversion | May 4, 1998 | Issued |
Array
(
[id] => 4161411
[patent_doc_number] => 06032170
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-29
[patent_title] => 'Long instruction word controlling plural independent processor operations'
[patent_app_type] => 1
[patent_app_number] => 9/063318
[patent_app_country] => US
[patent_app_date] => 1998-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 70
[patent_no_of_words] => 98154
[patent_no_of_claims] => 65
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/032/06032170.pdf
[firstpage_image] =>[orig_patent_app_number] => 063318
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/063318 | Long instruction word controlling plural independent processor operations | Apr 19, 1998 | Issued |