Tan V. Mai

Array ( [id] => 4137742 [patent_doc_number] => 06073149 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Computational circuit' [patent_app_type] => 1 [patent_app_number] => 9/060000 [patent_app_country] => US [patent_app_date] => 1998-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 5311 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 370 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073149.pdf [firstpage_image] =>[orig_patent_app_number] => 060000 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4170699 [patent_doc_number] => 06125380 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Dividing method' [patent_app_type] => 1 [patent_app_number] => 9/059931 [patent_app_country] => US [patent_app_date] => 1998-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 3 [patent_no_of_words] => 3356 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125380.pdf [firstpage_image] =>[orig_patent_app_number] => 059931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4267986 [patent_doc_number] => 06138137 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Methods and apparatus for performing fast division operations in bit-serial processors' [patent_app_type] => 1 [patent_app_number] => 9/057572 [patent_app_country] => US [patent_app_date] => 1998-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3041 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138137.pdf [firstpage_image] =>[orig_patent_app_number] => 057572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4020681 [patent_doc_number] => 05987484 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Digital filtering system' [patent_app_type] => 1 [patent_app_number] => 9/056228 [patent_app_country] => US [patent_app_date] => 1998-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 9210 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987484.pdf [firstpage_image] =>[orig_patent_app_number] => 056228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4146492 [patent_doc_number] => 06128637 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Arithmetic unit and operating method' [patent_app_type] => 1 [patent_app_number] => 9/055218 [patent_app_country] => US [patent_app_date] => 1998-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7550 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128637.pdf [firstpage_image] =>[orig_patent_app_number] => 055218 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4411619 [patent_doc_number] => 06298367 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Floating point addition pipeline including extreme value, comparison and accumulate functions' [patent_app_type] => 1 [patent_app_number] => 9/055916 [patent_app_country] => US [patent_app_date] => 1998-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 88 [patent_no_of_words] => 32152 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298367.pdf [firstpage_image] =>[orig_patent_app_number] => 055916 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4316814 [patent_doc_number] => 06185596 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Apparatus & method for modular multiplication & exponentiation based on Montgomery multiplication' [patent_app_type] => 1 [patent_app_number] => 9/050958 [patent_app_country] => US [patent_app_date] => 1998-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11894 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 433 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185596.pdf [firstpage_image] =>[orig_patent_app_number] => 050958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4259186 [patent_doc_number] => 06167419 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Multiplication method and multiplication circuit' [patent_app_type] => 1 [patent_app_number] => 9/052064 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7888 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/167/06167419.pdf [firstpage_image] =>[orig_patent_app_number] => 052064 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4150922 [patent_doc_number] => 06035318 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Booth multiplier for handling variable width operands' [patent_app_type] => 1 [patent_app_number] => 9/050993 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7376 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035318.pdf [firstpage_image] =>[orig_patent_app_number] => 050993 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4206129 [patent_doc_number] => 06131108 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Apparatus, and associated method, for generating multi-bit length sequences' [patent_app_type] => 1 [patent_app_number] => 9/052890 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3035 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/131/06131108.pdf [firstpage_image] =>[orig_patent_app_number] => 052890 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4151608 [patent_doc_number] => 06148313 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Correlator method and apparatus' [patent_app_type] => 1 [patent_app_number] => 9/050114 [patent_app_country] => US [patent_app_date] => 1998-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 4 [patent_no_of_words] => 6809 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148313.pdf [firstpage_image] =>[orig_patent_app_number] => 050114 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4236364 [patent_doc_number] => 06112218 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Digital filter with efficient quantization circuitry' [patent_app_type] => 1 [patent_app_number] => 9/050391 [patent_app_country] => US [patent_app_date] => 1998-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 13820 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112218.pdf [firstpage_image] =>[orig_patent_app_number] => 050391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4166211 [patent_doc_number] => 06065030 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Method and apparatus for implementing short-word division techniques in a multiple modulus conversion context' [patent_app_type] => 1 [patent_app_number] => 9/050263 [patent_app_country] => US [patent_app_date] => 1998-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6951 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/065/06065030.pdf [firstpage_image] =>[orig_patent_app_number] => 050263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4201776 [patent_doc_number] => 06094668 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Floating point arithmetic unit including an efficient close data path' [patent_app_type] => 1 [patent_app_number] => 9/049893 [patent_app_country] => US [patent_app_date] => 1998-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 88 [patent_no_of_words] => 32115 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094668.pdf [firstpage_image] =>[orig_patent_app_number] => 049893 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4193766 [patent_doc_number] => 06085212 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Efficient method for performing close path subtraction in a floating point arithmetic unit' [patent_app_type] => 1 [patent_app_number] => 9/049863 [patent_app_country] => US [patent_app_date] => 1998-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 88 [patent_no_of_words] => 32115 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085212.pdf [firstpage_image] =>[orig_patent_app_number] => 049863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4198129 [patent_doc_number] => 06038583 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Method and apparatus for simultaneously multiplying two or more independent pairs of operands and calculating a rounded products' [patent_app_type] => 1 [patent_app_number] => 9/049854 [patent_app_country] => US [patent_app_date] => 1998-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 30 [patent_no_of_words] => 15329 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038583.pdf [firstpage_image] =>[orig_patent_app_number] => 049854 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3960424 [patent_doc_number] => 05974434 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Method and apparatus for automatically tuning the parameters of a feedback control system' [patent_app_type] => 1 [patent_app_number] => 9/048018 [patent_app_country] => US [patent_app_date] => 1998-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 6750 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974434.pdf [firstpage_image] =>[orig_patent_app_number] => 048018 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4256169 [patent_doc_number] => 06081822 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Approximating signal power and noise power in a system' [patent_app_type] => 1 [patent_app_number] => 9/038082 [patent_app_country] => US [patent_app_date] => 1998-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6372 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081822.pdf [firstpage_image] =>[orig_patent_app_number] => 038082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4199237 [patent_doc_number] => 06021422 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Partitioning of binary quad word format multiply instruction on S/390 processor' [patent_app_type] => 1 [patent_app_number] => 9/033626 [patent_app_country] => US [patent_app_date] => 1998-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3538 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 565 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/021/06021422.pdf [firstpage_image] =>[orig_patent_app_number] => 033626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4259134 [patent_doc_number] => 06167415 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Recursive digital filter with reset' [patent_app_type] => 1 [patent_app_number] => 9/027912 [patent_app_country] => US [patent_app_date] => 1998-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 38 [patent_no_of_words] => 20265 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/167/06167415.pdf [firstpage_image] =>[orig_patent_app_number] => 027912 [rel_patent_id] =>[rel_patent_doc_number] =>)