Tan V. Mai

Array ( [id] => 4178103 [patent_doc_number] => 06115728 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Fast fourier transforming apparatus and method, variable bit reverse circuit, inverse fast fourier transforming apparatus and method, and OFDM receiver and transmitter' [patent_app_type] => 1 [patent_app_number] => 9/010499 [patent_app_country] => US [patent_app_date] => 1998-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 46 [patent_no_of_words] => 15751 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115728.pdf [firstpage_image] =>[orig_patent_app_number] => 010499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4159499 [patent_doc_number] => 06061705 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Power and area efficient fast fourier transform processor' [patent_app_type] => 1 [patent_app_number] => 9/010130 [patent_app_country] => US [patent_app_date] => 1998-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 7411 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061705.pdf [firstpage_image] =>[orig_patent_app_number] => 010130 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4103025 [patent_doc_number] => 06026420 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'High-speed evaluation of polynomials' [patent_app_type] => 1 [patent_app_number] => 9/009393 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5003 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026420.pdf [firstpage_image] =>[orig_patent_app_number] => 009393 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4225128 [patent_doc_number] => 06029186 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'High speed calculation of cyclical redundancy check sums' [patent_app_type] => 1 [patent_app_number] => 9/009069 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6539 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/029/06029186.pdf [firstpage_image] =>[orig_patent_app_number] => 009069 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4198046 [patent_doc_number] => 06038577 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Efficient way to produce a delayed version of a maximum length sequence using a division circuit' [patent_app_type] => 1 [patent_app_number] => 9/005032 [patent_app_country] => US [patent_app_date] => 1998-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5101 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038577.pdf [firstpage_image] =>[orig_patent_app_number] => 005032 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4150908 [patent_doc_number] => 06035317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Modular arithmetic coprocessor comprising two multiplication circuits working in parallel' [patent_app_type] => 1 [patent_app_number] => 9/004375 [patent_app_country] => US [patent_app_date] => 1998-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 15264 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035317.pdf [firstpage_image] =>[orig_patent_app_number] => 004375 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4201762 [patent_doc_number] => 06094667 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Time spread root Nyquist filter' [patent_app_type] => 1 [patent_app_number] => 9/003507 [patent_app_country] => US [patent_app_date] => 1998-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2081 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094667.pdf [firstpage_image] =>[orig_patent_app_number] => 003507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4056550 [patent_doc_number] => 05995993 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Serial in-circuit emulator' [patent_app_type] => 1 [patent_app_number] => 9/003064 [patent_app_country] => US [patent_app_date] => 1998-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3850 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/995/05995993.pdf [firstpage_image] =>[orig_patent_app_number] => 003064 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4239372 [patent_doc_number] => 06012076 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Arithmetic logic unit having preshift and preround circuits' [patent_app_type] => 1 [patent_app_number] => 8/998562 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2797 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/012/06012076.pdf [firstpage_image] =>[orig_patent_app_number] => 998562 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3915463 [patent_doc_number] => 05951631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Carry lookahead adder' [patent_app_type] => 1 [patent_app_number] => 8/999259 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3906 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/951/05951631.pdf [firstpage_image] =>[orig_patent_app_number] => 999259 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4210500 [patent_doc_number] => 06044389 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'System for computing the multiplicative inverse of a field element for galois fields without using tables' [patent_app_type] => 1 [patent_app_number] => 8/999038 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5142 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044389.pdf [firstpage_image] =>[orig_patent_app_number] => 999038 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4113893 [patent_doc_number] => 06049814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Spectrum feature parameter extracting system based on frequency weight estimation function' [patent_app_type] => 1 [patent_app_number] => 8/999396 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2253 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049814.pdf [firstpage_image] =>[orig_patent_app_number] => 999396 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1338667 [patent_doc_number] => 06601079 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Converting between different floating point exponent representations' [patent_app_type] => B1 [patent_app_number] => 08/998617 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4655 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/601/06601079.pdf [firstpage_image] =>[orig_patent_app_number] => 08998617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4099149 [patent_doc_number] => 06055555 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Interface for performing parallel arithmetic and round operations' [patent_app_type] => 1 [patent_app_number] => 8/999243 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3560 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055555.pdf [firstpage_image] =>[orig_patent_app_number] => 999243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3931879 [patent_doc_number] => 06003057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Galois field arithmetic logic unit circuit' [patent_app_type] => 1 [patent_app_number] => 8/998376 [patent_app_country] => US [patent_app_date] => 1997-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6417 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/003/06003057.pdf [firstpage_image] =>[orig_patent_app_number] => 998376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4424343 [patent_doc_number] => 06230179 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Finite field multiplier with intrinsic modular reduction' [patent_app_type] => 1 [patent_app_number] => 8/997960 [patent_app_country] => US [patent_app_date] => 1997-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 7072 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230179.pdf [firstpage_image] =>[orig_patent_app_number] => 997960 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4113907 [patent_doc_number] => 06049815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Method and apparatus for finite field multiplication' [patent_app_type] => 1 [patent_app_number] => 8/997673 [patent_app_country] => US [patent_app_date] => 1997-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5093 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049815.pdf [firstpage_image] =>[orig_patent_app_number] => 997673 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4084454 [patent_doc_number] => 06009450 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Finite field inverse circuit' [patent_app_type] => 1 [patent_app_number] => 8/997943 [patent_app_country] => US [patent_app_date] => 1997-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7352 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009450.pdf [firstpage_image] =>[orig_patent_app_number] => 997943 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4159485 [patent_doc_number] => 06061704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Method and apparatus for rate conversion' [patent_app_type] => 1 [patent_app_number] => 8/996626 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2149 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061704.pdf [firstpage_image] =>[orig_patent_app_number] => 996626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4214860 [patent_doc_number] => 06014683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Arithmetic operation system for arithmetically operating a first operand having an actual point and a second operand having no actual point' [patent_app_type] => 1 [patent_app_number] => 8/995861 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7408 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014683.pdf [firstpage_image] =>[orig_patent_app_number] => 995861 [rel_patent_id] =>[rel_patent_doc_number] =>)