Search

Tan V. Mai

Examiner (ID: 15743)

Most Active Art Unit
2193
Art Unit(s)
2306, 2193, 2787, 2786, 2121, 2124, 2302, 2301, 2182, 2183
Total Applications
3863
Issued Applications
3431
Pending Applications
94
Abandoned Applications
349

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4019062 [patent_doc_number] => 05889692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Fast determination of carry inputs from lower order product for radix-8 odd/even multiplier array' [patent_app_type] => 1 [patent_app_number] => 8/938951 [patent_app_country] => US [patent_app_date] => 1997-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10825 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889692.pdf [firstpage_image] =>[orig_patent_app_number] => 938951 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/938951
Fast determination of carry inputs from lower order product for radix-8 odd/even multiplier array Sep 17, 1997 Issued
Array ( [id] => 3986258 [patent_doc_number] => 05905662 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Digital processing system for binary addition/subtraction' [patent_app_type] => 1 [patent_app_number] => 8/927210 [patent_app_country] => US [patent_app_date] => 1997-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4321 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905662.pdf [firstpage_image] =>[orig_patent_app_number] => 927210 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/927210
Digital processing system for binary addition/subtraction Sep 10, 1997 Issued
Array ( [id] => 3914825 [patent_doc_number] => 05944771 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Arithmetic operation system for binary addition/subtraction' [patent_app_type] => 1 [patent_app_number] => 8/927806 [patent_app_country] => US [patent_app_date] => 1997-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 5628 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/944/05944771.pdf [firstpage_image] =>[orig_patent_app_number] => 927806 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/927806
Arithmetic operation system for binary addition/subtraction Sep 10, 1997 Issued
Array ( [id] => 4019010 [patent_doc_number] => 05889689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Hierarchical carry-select, three-input saturation' [patent_app_type] => 1 [patent_app_number] => 8/927558 [patent_app_country] => US [patent_app_date] => 1997-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2137 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889689.pdf [firstpage_image] =>[orig_patent_app_number] => 927558 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/927558
Hierarchical carry-select, three-input saturation Sep 7, 1997 Issued
Array ( [id] => 4036103 [patent_doc_number] => 05968112 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Signal processor and method for Fourier Transformation' [patent_app_type] => 1 [patent_app_number] => 8/923845 [patent_app_country] => US [patent_app_date] => 1997-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5637 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968112.pdf [firstpage_image] =>[orig_patent_app_number] => 923845 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/923845
Signal processor and method for Fourier Transformation Sep 3, 1997 Issued
Array ( [id] => 4027012 [patent_doc_number] => 05907496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Multiplication and addition circuit' [patent_app_type] => 1 [patent_app_number] => 8/921578 [patent_app_country] => US [patent_app_date] => 1997-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3122 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907496.pdf [firstpage_image] =>[orig_patent_app_number] => 921578 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/921578
Multiplication and addition circuit Sep 1, 1997 Issued
Array ( [id] => 1432334 [patent_doc_number] => 06505226 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'High speed parallel adder' [patent_app_type] => B1 [patent_app_number] => 08/921701 [patent_app_country] => US [patent_app_date] => 1997-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 3891 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505226.pdf [firstpage_image] =>[orig_patent_app_number] => 08921701 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/921701
High speed parallel adder Sep 1, 1997 Issued
Array ( [id] => 4269287 [patent_doc_number] => 06223197 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Constant multiplier, method and device for automatically providing constant multiplier and storage medium storing constant multiplier automatic providing program' [patent_app_type] => 1 [patent_app_number] => 8/916414 [patent_app_country] => US [patent_app_date] => 1997-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 11489 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223197.pdf [firstpage_image] =>[orig_patent_app_number] => 916414 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/916414
Constant multiplier, method and device for automatically providing constant multiplier and storage medium storing constant multiplier automatic providing program Aug 21, 1997 Issued
Array ( [id] => 4084426 [patent_doc_number] => 06009448 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Pipelined parallel-serial architecture for a modified least mean square adaptive filter' [patent_app_type] => 1 [patent_app_number] => 8/912591 [patent_app_country] => US [patent_app_date] => 1997-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 3239 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009448.pdf [firstpage_image] =>[orig_patent_app_number] => 912591 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/912591
Pipelined parallel-serial architecture for a modified least mean square adaptive filter Aug 17, 1997 Issued
Array ( [id] => 3969452 [patent_doc_number] => 05958002 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Vector absolute--value calculation circuit' [patent_app_type] => 1 [patent_app_number] => 8/905784 [patent_app_country] => US [patent_app_date] => 1997-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 9963 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/958/05958002.pdf [firstpage_image] =>[orig_patent_app_number] => 905784 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/905784
Vector absolute--value calculation circuit Aug 11, 1997 Issued
Array ( [id] => 3939628 [patent_doc_number] => 05877974 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Folded analog signal multiplier circuit' [patent_app_type] => 1 [patent_app_number] => 8/909025 [patent_app_country] => US [patent_app_date] => 1997-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2046 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877974.pdf [firstpage_image] =>[orig_patent_app_number] => 909025 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/909025
Folded analog signal multiplier circuit Aug 10, 1997 Issued
Array ( [id] => 3774651 [patent_doc_number] => 05844828 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Shift circuit and system having the same' [patent_app_type] => 1 [patent_app_number] => 8/905276 [patent_app_country] => US [patent_app_date] => 1997-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 7120 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844828.pdf [firstpage_image] =>[orig_patent_app_number] => 905276 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/905276
Shift circuit and system having the same Aug 5, 1997 Issued
Array ( [id] => 3897474 [patent_doc_number] => 06000834 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Audio sampling rate conversion filter' [patent_app_type] => 1 [patent_app_number] => 8/907314 [patent_app_country] => US [patent_app_date] => 1997-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4387 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000834.pdf [firstpage_image] =>[orig_patent_app_number] => 907314 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/907314
Audio sampling rate conversion filter Aug 5, 1997 Issued
Array ( [id] => 3986305 [patent_doc_number] => 05905665 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Modulo address generating circuit and method with reduced area and delay using low speed adders' [patent_app_type] => 1 [patent_app_number] => 8/906273 [patent_app_country] => US [patent_app_date] => 1997-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2232 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905665.pdf [firstpage_image] =>[orig_patent_app_number] => 906273 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/906273
Modulo address generating circuit and method with reduced area and delay using low speed adders Aug 4, 1997 Issued
Array ( [id] => 4311503 [patent_doc_number] => 06237016 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Method and apparatus for multiplying and accumulating data samples and complex coefficients' [patent_app_type] => 1 [patent_app_number] => 8/905506 [patent_app_country] => US [patent_app_date] => 1997-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 14282 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/237/06237016.pdf [firstpage_image] =>[orig_patent_app_number] => 905506 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/905506
Method and apparatus for multiplying and accumulating data samples and complex coefficients Jul 30, 1997 Issued
Array ( [id] => 3845233 [patent_doc_number] => 05815420 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Microprocessor arithmetic logic unit using multiple number representations' [patent_app_type] => 1 [patent_app_number] => 8/903846 [patent_app_country] => US [patent_app_date] => 1997-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8994 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815420.pdf [firstpage_image] =>[orig_patent_app_number] => 903846 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/903846
Microprocessor arithmetic logic unit using multiple number representations Jul 30, 1997 Issued
Array ( [id] => 3987315 [patent_doc_number] => 05922043 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Reduced hardware linear interpolator' [patent_app_type] => 1 [patent_app_number] => 8/902762 [patent_app_country] => US [patent_app_date] => 1997-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1826 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/922/05922043.pdf [firstpage_image] =>[orig_patent_app_number] => 902762 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/902762
Reduced hardware linear interpolator Jul 29, 1997 Issued
Array ( [id] => 4137828 [patent_doc_number] => 06073155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Floating-point accumulator' [patent_app_type] => 1 [patent_app_number] => 8/901671 [patent_app_country] => US [patent_app_date] => 1997-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 13120 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073155.pdf [firstpage_image] =>[orig_patent_app_number] => 901671 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/901671
Floating-point accumulator Jul 27, 1997 Issued
Array ( [id] => 3896180 [patent_doc_number] => 05894428 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Recursive digital filter' [patent_app_type] => 1 [patent_app_number] => 8/901782 [patent_app_country] => US [patent_app_date] => 1997-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5833 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894428.pdf [firstpage_image] =>[orig_patent_app_number] => 901782 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/901782
Recursive digital filter Jul 27, 1997 Issued
Array ( [id] => 4054283 [patent_doc_number] => 05912831 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Process and system for adding or substracting symbols in any base without converting to a common base' [patent_app_type] => 1 [patent_app_number] => 8/897170 [patent_app_country] => US [patent_app_date] => 1997-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 11051 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912831.pdf [firstpage_image] =>[orig_patent_app_number] => 897170 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/897170
Process and system for adding or substracting symbols in any base without converting to a common base Jul 17, 1997 Issued
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