
Tan V. Mai
Examiner (ID: 15743)
| Most Active Art Unit | 2193 |
| Art Unit(s) | 2306, 2193, 2787, 2786, 2121, 2124, 2302, 2301, 2182, 2183 |
| Total Applications | 3863 |
| Issued Applications | 3431 |
| Pending Applications | 94 |
| Abandoned Applications | 349 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4084440
[patent_doc_number] => 06009449
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-28
[patent_title] => 'Phase angle data-trigonometric function value converter circuit and composite diversity receiver'
[patent_app_type] => 1
[patent_app_number] => 8/895262
[patent_app_country] => US
[patent_app_date] => 1997-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2855
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/009/06009449.pdf
[firstpage_image] =>[orig_patent_app_number] => 895262
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/895262 | Phase angle data-trigonometric function value converter circuit and composite diversity receiver | Jul 15, 1997 | Issued |
Array
(
[id] => 3950259
[patent_doc_number] => 05930157
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-27
[patent_title] => 'Autocorrelation coefficient operator having analog circuit element'
[patent_app_type] => 1
[patent_app_number] => 8/895272
[patent_app_country] => US
[patent_app_date] => 1997-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 3712
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/930/05930157.pdf
[firstpage_image] =>[orig_patent_app_number] => 895272
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/895272 | Autocorrelation coefficient operator having analog circuit element | Jul 15, 1997 | Issued |
Array
(
[id] => 4054401
[patent_doc_number] => 05875125
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-23
[patent_title] => 'X+2X adder with multi-bit generate/propagate circuit'
[patent_app_type] => 1
[patent_app_number] => 8/888254
[patent_app_country] => US
[patent_app_date] => 1997-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 22
[patent_no_of_words] => 3323
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/875/05875125.pdf
[firstpage_image] =>[orig_patent_app_number] => 888254
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/888254 | X+2X adder with multi-bit generate/propagate circuit | Jul 6, 1997 | Issued |
Array
(
[id] => 3915356
[patent_doc_number] => 05951625
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-14
[patent_title] => 'Interpolated lookup table circuit'
[patent_app_type] => 1
[patent_app_number] => 8/885249
[patent_app_country] => US
[patent_app_date] => 1997-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8033
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/951/05951625.pdf
[firstpage_image] =>[orig_patent_app_number] => 885249
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/885249 | Interpolated lookup table circuit | Jun 29, 1997 | Issued |
Array
(
[id] => 3944602
[patent_doc_number] => 05935199
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-10
[patent_title] => 'Dc accurate multi-rate digital filter with common coefficient set and dc gain correction'
[patent_app_type] => 1
[patent_app_number] => 8/883952
[patent_app_country] => US
[patent_app_date] => 1997-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 3777
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/935/05935199.pdf
[firstpage_image] =>[orig_patent_app_number] => 883952
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/883952 | Dc accurate multi-rate digital filter with common coefficient set and dc gain correction | Jun 26, 1997 | Issued |
Array
(
[id] => 4072950
[patent_doc_number] => 05896304
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-20
[patent_title] => 'Low power parallel correlator for measuring correlation between digital signal segments'
[patent_app_type] => 1
[patent_app_number] => 8/883161
[patent_app_country] => US
[patent_app_date] => 1997-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 23
[patent_no_of_words] => 13226
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/896/05896304.pdf
[firstpage_image] =>[orig_patent_app_number] => 883161
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/883161 | Low power parallel correlator for measuring correlation between digital signal segments | Jun 25, 1997 | Issued |
Array
(
[id] => 3996455
[patent_doc_number] => 05961578
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-05
[patent_title] => 'Data processor and microcomputer'
[patent_app_type] => 1
[patent_app_number] => 8/883235
[patent_app_country] => US
[patent_app_date] => 1997-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 10016
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/961/05961578.pdf
[firstpage_image] =>[orig_patent_app_number] => 883235
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/883235 | Data processor and microcomputer | Jun 25, 1997 | Issued |
Array
(
[id] => 4210527
[patent_doc_number] => 06044391
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-28
[patent_title] => 'Method of generating the sticky-bit from the input operands'
[patent_app_type] => 1
[patent_app_number] => 8/883119
[patent_app_country] => US
[patent_app_date] => 1997-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 7458
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 531
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/044/06044391.pdf
[firstpage_image] =>[orig_patent_app_number] => 883119
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/883119 | Method of generating the sticky-bit from the input operands | Jun 24, 1997 | Issued |
Array
(
[id] => 3791837
[patent_doc_number] => 05818747
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-06
[patent_title] => 'Small, fast CMOS 4-2 carry-save adder cell'
[patent_app_type] => 1
[patent_app_number] => 8/882364
[patent_app_country] => US
[patent_app_date] => 1997-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 3457
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/818/05818747.pdf
[firstpage_image] =>[orig_patent_app_number] => 882364
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/882364 | Small, fast CMOS 4-2 carry-save adder cell | Jun 24, 1997 | Issued |
Array
(
[id] => 3914863
[patent_doc_number] => 05944773
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-31
[patent_title] => 'Floating-point multiplier circuit for generating the sticky-bit from the input operands'
[patent_app_type] => 1
[patent_app_number] => 8/881702
[patent_app_country] => US
[patent_app_date] => 1997-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 7234
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 531
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/944/05944773.pdf
[firstpage_image] =>[orig_patent_app_number] => 881702
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/881702 | Floating-point multiplier circuit for generating the sticky-bit from the input operands | Jun 24, 1997 | Issued |
Array
(
[id] => 4072991
[patent_doc_number] => 05896307
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-20
[patent_title] => 'Method for handling an underflow condition in a processor'
[patent_app_type] => 1
[patent_app_number] => 8/880628
[patent_app_country] => US
[patent_app_date] => 1997-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2189
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 20
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/896/05896307.pdf
[firstpage_image] =>[orig_patent_app_number] => 880628
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/880628 | Method for handling an underflow condition in a processor | Jun 22, 1997 | Issued |
Array
(
[id] => 3986244
[patent_doc_number] => 05905661
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-18
[patent_title] => 'Method for handling an overflow condition in a processor'
[patent_app_type] => 1
[patent_app_number] => 8/880631
[patent_app_country] => US
[patent_app_date] => 1997-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2215
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 20
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/905/05905661.pdf
[firstpage_image] =>[orig_patent_app_number] => 880631
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/880631 | Method for handling an overflow condition in a processor | Jun 22, 1997 | Issued |
Array
(
[id] => 3802060
[patent_doc_number] => 05841679
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-24
[patent_title] => 'Vector computation device and vector computation method'
[patent_app_type] => 1
[patent_app_number] => 8/867415
[patent_app_country] => US
[patent_app_date] => 1997-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 6617
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/841/05841679.pdf
[firstpage_image] =>[orig_patent_app_number] => 867415
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/867415 | Vector computation device and vector computation method | Jun 1, 1997 | Issued |
Array
(
[id] => 3820999
[patent_doc_number] => 05831888
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-03
[patent_title] => 'Automatic gain control circuit and method'
[patent_app_type] => 1
[patent_app_number] => 8/859964
[patent_app_country] => US
[patent_app_date] => 1997-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 4089
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/831/05831888.pdf
[firstpage_image] =>[orig_patent_app_number] => 859964
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/859964 | Automatic gain control circuit and method | May 20, 1997 | Issued |
Array
(
[id] => 4164748
[patent_doc_number] => 06036350
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-14
[patent_title] => 'Method of sorting signed numbers and solving absolute differences using packed instructions'
[patent_app_type] => 1
[patent_app_number] => 8/859013
[patent_app_country] => US
[patent_app_date] => 1997-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 6956
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/036/06036350.pdf
[firstpage_image] =>[orig_patent_app_number] => 859013
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/859013 | Method of sorting signed numbers and solving absolute differences using packed instructions | May 19, 1997 | Issued |
Array
(
[id] => 3896206
[patent_doc_number] => 05894430
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-13
[patent_title] => 'Orthogonal transform processor'
[patent_app_type] => 1
[patent_app_number] => 8/859785
[patent_app_country] => US
[patent_app_date] => 1997-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 5958
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/894/05894430.pdf
[firstpage_image] =>[orig_patent_app_number] => 859785
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/859785 | Orthogonal transform processor | May 18, 1997 | Issued |
Array
(
[id] => 4054371
[patent_doc_number] => 05875123
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-23
[patent_title] => 'Carry-select adder with pre-counting of leading zero digits'
[patent_app_type] => 1
[patent_app_number] => 8/765419
[patent_app_country] => US
[patent_app_date] => 1997-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 16
[patent_no_of_words] => 5671
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/875/05875123.pdf
[firstpage_image] =>[orig_patent_app_number] => 765419
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/765419 | Carry-select adder with pre-counting of leading zero digits | May 12, 1997 | Issued |
Array
(
[id] => 3922784
[patent_doc_number] => 05928313
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-27
[patent_title] => 'Method and apparatus for sample rate conversion'
[patent_app_type] => 1
[patent_app_number] => 8/841891
[patent_app_country] => US
[patent_app_date] => 1997-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 8038
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/928/05928313.pdf
[firstpage_image] =>[orig_patent_app_number] => 841891
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/841891 | Method and apparatus for sample rate conversion | May 4, 1997 | Issued |
Array
(
[id] => 4034278
[patent_doc_number] => 05926406
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-20
[patent_title] => 'System and method for calculating floating point exponential values in a geometry accelerator'
[patent_app_type] => 1
[patent_app_number] => 8/847645
[patent_app_country] => US
[patent_app_date] => 1997-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 9168
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/926/05926406.pdf
[firstpage_image] =>[orig_patent_app_number] => 847645
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/847645 | System and method for calculating floating point exponential values in a geometry accelerator | Apr 29, 1997 | Issued |
Array
(
[id] => 4054269
[patent_doc_number] => 05912830
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-15
[patent_title] => 'System and method for conditionally calculating exponential values in a geometry accelerator'
[patent_app_type] => 1
[patent_app_number] => 8/846365
[patent_app_country] => US
[patent_app_date] => 1997-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 8734
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/912/05912830.pdf
[firstpage_image] =>[orig_patent_app_number] => 846365
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/846365 | System and method for conditionally calculating exponential values in a geometry accelerator | Apr 29, 1997 | Issued |