Search

Tan V. Mai

Examiner (ID: 15743)

Most Active Art Unit
2193
Art Unit(s)
2306, 2193, 2787, 2786, 2121, 2124, 2302, 2301, 2182, 2183
Total Applications
3863
Issued Applications
3431
Pending Applications
94
Abandoned Applications
349

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3931906 [patent_doc_number] => 06003059 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Carry select adder using two level selectors' [patent_app_type] => 1 [patent_app_number] => 8/804703 [patent_app_country] => US [patent_app_date] => 1997-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8887 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/003/06003059.pdf [firstpage_image] =>[orig_patent_app_number] => 804703 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/804703
Carry select adder using two level selectors Feb 20, 1997 Issued
Array ( [id] => 3993533 [patent_doc_number] => 05862065 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Method and circuit for fast generation of zero flag condition code in a microprocessor-based computer' [patent_app_type] => 1 [patent_app_number] => 8/799452 [patent_app_country] => US [patent_app_date] => 1997-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3527 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/862/05862065.pdf [firstpage_image] =>[orig_patent_app_number] => 799452 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/799452
Method and circuit for fast generation of zero flag condition code in a microprocessor-based computer Feb 12, 1997 Issued
Array ( [id] => 4064127 [patent_doc_number] => 05933362 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Method of adding two binary numbers and binary adder used therein' [patent_app_type] => 1 [patent_app_number] => 8/797121 [patent_app_country] => US [patent_app_date] => 1997-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5650 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 415 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933362.pdf [firstpage_image] =>[orig_patent_app_number] => 797121 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/797121
Method of adding two binary numbers and binary adder used therein Feb 9, 1997 Issued
Array ( [id] => 4072964 [patent_doc_number] => 05896305 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Shifter circuit for an arithmetic logic unit in a microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/796311 [patent_app_country] => US [patent_app_date] => 1997-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 10967 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896305.pdf [firstpage_image] =>[orig_patent_app_number] => 796311 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/796311
Shifter circuit for an arithmetic logic unit in a microprocessor Feb 6, 1997 Issued
Array ( [id] => 4005071 [patent_doc_number] => 05920498 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Compression circuit of an adder circuit' [patent_app_type] => 1 [patent_app_number] => 8/794495 [patent_app_country] => US [patent_app_date] => 1997-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 10637 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920498.pdf [firstpage_image] =>[orig_patent_app_number] => 794495 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/794495
Compression circuit of an adder circuit Feb 3, 1997 Issued
Array ( [id] => 3962079 [patent_doc_number] => 05956263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Multiplication, division and square root extraction apparatus' [patent_app_type] => 1 [patent_app_number] => 8/797653 [patent_app_country] => US [patent_app_date] => 1997-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 28 [patent_no_of_words] => 13500 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956263.pdf [firstpage_image] =>[orig_patent_app_number] => 797653 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/797653
Multiplication, division and square root extraction apparatus Jan 30, 1997 Issued
Array ( [id] => 4109004 [patent_doc_number] => 06134569 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Polyphase interpolator/decimator using continuous-valued, discrete-time signal processing' [patent_app_type] => 1 [patent_app_number] => 8/789952 [patent_app_country] => US [patent_app_date] => 1997-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2541 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134569.pdf [firstpage_image] =>[orig_patent_app_number] => 789952 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/789952
Polyphase interpolator/decimator using continuous-valued, discrete-time signal processing Jan 29, 1997 Issued
Array ( [id] => 3904609 [patent_doc_number] => 05835387 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Multiplication circuit' [patent_app_type] => 1 [patent_app_number] => 8/791022 [patent_app_country] => US [patent_app_date] => 1997-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5788 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835387.pdf [firstpage_image] =>[orig_patent_app_number] => 791022 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/791022
Multiplication circuit Jan 26, 1997 Issued
Array ( [id] => 3845265 [patent_doc_number] => 05815422 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Computer-implemented multiplication with shifting of pattern-product partials' [patent_app_type] => 1 [patent_app_number] => 8/789156 [patent_app_country] => US [patent_app_date] => 1997-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3850 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815422.pdf [firstpage_image] =>[orig_patent_app_number] => 789156 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/789156
Computer-implemented multiplication with shifting of pattern-product partials Jan 23, 1997 Issued
Array ( [id] => 4034308 [patent_doc_number] => 05926408 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Bipolar multiplier with wide input voltage range using multitail cell' [patent_app_type] => 1 [patent_app_number] => 8/783848 [patent_app_country] => US [patent_app_date] => 1997-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 58 [patent_no_of_words] => 18409 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 389 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926408.pdf [firstpage_image] =>[orig_patent_app_number] => 783848 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/783848
Bipolar multiplier with wide input voltage range using multitail cell Jan 15, 1997 Issued
Array ( [id] => 3939599 [patent_doc_number] => 05877972 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'High speed incrementer with array method' [patent_app_type] => 1 [patent_app_number] => 8/783979 [patent_app_country] => US [patent_app_date] => 1997-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2846 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877972.pdf [firstpage_image] =>[orig_patent_app_number] => 783979 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/783979
High speed incrementer with array method Jan 14, 1997 Issued
Array ( [id] => 4099174 [patent_doc_number] => 06055557 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Adder circuit and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/780561 [patent_app_country] => US [patent_app_date] => 1997-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7954 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055557.pdf [firstpage_image] =>[orig_patent_app_number] => 780561 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/780561
Adder circuit and method therefor Jan 7, 1997 Issued
Array ( [id] => 3900580 [patent_doc_number] => 05777916 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Method for the production of an error correction parameter associated with the implementation of modular operations according to the montgomery method' [patent_app_type] => 1 [patent_app_number] => 8/779525 [patent_app_country] => US [patent_app_date] => 1997-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4825 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/777/05777916.pdf [firstpage_image] =>[orig_patent_app_number] => 779525 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/779525
Method for the production of an error correction parameter associated with the implementation of modular operations according to the montgomery method Jan 6, 1997 Issued
Array ( [id] => 3993506 [patent_doc_number] => 05862063 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Enhanced wavetable processing technique on a vector processor having operand routing and slot selectable operations' [patent_app_type] => 1 [patent_app_number] => 8/770346 [patent_app_country] => US [patent_app_date] => 1996-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 10676 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/862/05862063.pdf [firstpage_image] =>[orig_patent_app_number] => 770346 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/770346
Enhanced wavetable processing technique on a vector processor having operand routing and slot selectable operations Dec 19, 1996 Issued
Array ( [id] => 4054356 [patent_doc_number] => 05875122 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Integrated systolic architecture for decomposition and reconstruction of signals using wavelet transforms' [patent_app_type] => 1 [patent_app_number] => 8/767976 [patent_app_country] => US [patent_app_date] => 1996-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8388 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875122.pdf [firstpage_image] =>[orig_patent_app_number] => 767976 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/767976
Integrated systolic architecture for decomposition and reconstruction of signals using wavelet transforms Dec 16, 1996 Issued
Array ( [id] => 3802101 [patent_doc_number] => 05841682 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Inverse discrete cosine transformation system using Lee\'s algorithm' [patent_app_type] => 1 [patent_app_number] => 8/763611 [patent_app_country] => US [patent_app_date] => 1996-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10761 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841682.pdf [firstpage_image] =>[orig_patent_app_number] => 763611 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/763611
Inverse discrete cosine transformation system using Lee's algorithm Dec 10, 1996 Issued
Array ( [id] => 3756468 [patent_doc_number] => 05801975 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Computer modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instruction cycles' [patent_app_type] => 1 [patent_app_number] => 8/759045 [patent_app_country] => US [patent_app_date] => 1996-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 19465 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801975.pdf [firstpage_image] =>[orig_patent_app_number] => 759045 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/759045
Computer modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instruction cycles Dec 1, 1996 Issued
Array ( [id] => 4025548 [patent_doc_number] => 05941938 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'System and method for performing an accumulate operation on one or more operands within a partitioned register' [patent_app_type] => 1 [patent_app_number] => 8/759043 [patent_app_country] => US [patent_app_date] => 1996-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 20162 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/941/05941938.pdf [firstpage_image] =>[orig_patent_app_number] => 759043 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/759043
System and method for performing an accumulate operation on one or more operands within a partitioned register Dec 1, 1996 Issued
Array ( [id] => 3779996 [patent_doc_number] => 05850357 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-15 [patent_title] => 'Signal processing device' [patent_app_type] => 1 [patent_app_number] => 8/737780 [patent_app_country] => US [patent_app_date] => 1996-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3884 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/850/05850357.pdf [firstpage_image] =>[orig_patent_app_number] => 737780 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/737780
Signal processing device Nov 24, 1996 Issued
Array ( [id] => 3944587 [patent_doc_number] => 05935198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Multiplier with selectable booth encoders for performing 3D graphics interpolations with two multiplies in a single pass through the multiplier' [patent_app_type] => 1 [patent_app_number] => 8/755545 [patent_app_country] => US [patent_app_date] => 1996-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 7728 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/935/05935198.pdf [firstpage_image] =>[orig_patent_app_number] => 755545 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/755545
Multiplier with selectable booth encoders for performing 3D graphics interpolations with two multiplies in a single pass through the multiplier Nov 21, 1996 Issued
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