
Tan V. Mai
Examiner (ID: 15743)
| Most Active Art Unit | 2193 |
| Art Unit(s) | 2306, 2193, 2787, 2786, 2121, 2124, 2302, 2301, 2182, 2183 |
| Total Applications | 3863 |
| Issued Applications | 3431 |
| Pending Applications | 94 |
| Abandoned Applications | 349 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3837457
[patent_doc_number] => 05784304
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-21
[patent_title] => 'Adaptively controlled filter'
[patent_app_type] => 1
[patent_app_number] => 8/594172
[patent_app_country] => US
[patent_app_date] => 1996-01-31
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[patent_no_of_words] => 3477
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[pdf_file] => patents/05/784/05784304.pdf
[firstpage_image] =>[orig_patent_app_number] => 594172
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/594172 | Adaptively controlled filter | Jan 30, 1996 | Issued |
Array
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[patent_issue_date] => 1997-07-22
[patent_title] => 'Frequency and time domain adaptive filtration in a sampled communication channel'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/593824 | Frequency and time domain adaptive filtration in a sampled communication channel | Jan 29, 1996 | Issued |
Array
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[patent_issue_date] => 1998-01-06
[patent_title] => 'Interpolation device'
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[patent_app_date] => 1996-01-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/594036 | Interpolation device | Jan 29, 1996 | Issued |
Array
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[patent_issue_date] => 2000-06-27
[patent_title] => 'Semiconductor device, semiconductor circuit using the device, and correlation calculation device, signal converter, and signal processing system using the circuit'
[patent_app_type] => 1
[patent_app_number] => 8/592571
[patent_app_country] => US
[patent_app_date] => 1996-01-26
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[pdf_file] => patents/06/081/06081825.pdf
[firstpage_image] =>[orig_patent_app_number] => 592571
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/592571 | Semiconductor device, semiconductor circuit using the device, and correlation calculation device, signal converter, and signal processing system using the circuit | Jan 25, 1996 | Issued |
Array
(
[id] => 4067150
[patent_doc_number] => 05864495
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[patent_kind] => NA
[patent_issue_date] => 1999-01-26
[patent_title] => 'Arithmetic processing apparatus and arithmetic processing circuit'
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[firstpage_image] =>[orig_patent_app_number] => 591343
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/591343 | Arithmetic processing apparatus and arithmetic processing circuit | Jan 24, 1996 | Issued |
Array
(
[id] => 3915000
[patent_doc_number] => 05898602
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[patent_kind] => NA
[patent_issue_date] => 1999-04-27
[patent_title] => 'Carry chain circuit with flexible carry function for implementing arithmetic and logical functions'
[patent_app_type] => 1
[patent_app_number] => 8/591841
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/591841 | Carry chain circuit with flexible carry function for implementing arithmetic and logical functions | Jan 24, 1996 | Issued |
Array
(
[id] => 3889245
[patent_doc_number] => 05825681
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[patent_title] => 'Divider/multiplier circuit having high precision mode'
[patent_app_type] => 1
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[patent_app_country] => US
[patent_app_date] => 1996-01-24
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[pdf_file] => patents/05/825/05825681.pdf
[firstpage_image] =>[orig_patent_app_number] => 590656
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/590656 | Divider/multiplier circuit having high precision mode | Jan 23, 1996 | Issued |
Array
(
[id] => 3853514
[patent_doc_number] => 05745395
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-28
[patent_title] => 'Signal processing apparatus and method'
[patent_app_type] => 1
[patent_app_number] => 8/588397
[patent_app_country] => US
[patent_app_date] => 1996-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 3839
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[pdf_file] => patents/05/745/05745395.pdf
[firstpage_image] =>[orig_patent_app_number] => 588397
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/588397 | Signal processing apparatus and method | Jan 17, 1996 | Issued |
Array
(
[id] => 4401414
[patent_doc_number] => 06279024
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-21
[patent_title] => 'High performance, low power incrementer for dynamic circuits'
[patent_app_type] => 1
[patent_app_number] => 8/582716
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/582716 | High performance, low power incrementer for dynamic circuits | Jan 3, 1996 | Issued |
Array
(
[id] => 3873115
[patent_doc_number] => 05796643
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-18
[patent_title] => 'Logical operator based digital filter'
[patent_app_type] => 1
[patent_app_number] => 8/582002
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[pdf_file] => patents/05/796/05796643.pdf
[firstpage_image] =>[orig_patent_app_number] => 582002
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/582002 | Logical operator based digital filter | Jan 1, 1996 | Issued |
Array
(
[id] => 3697073
[patent_doc_number] => 05696710
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[patent_kind] => NA
[patent_issue_date] => 1997-12-09
[patent_title] => 'Apparatus for symmetrically reducing N least significant bits of an M-bit digital signal'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/581115 | Apparatus for symmetrically reducing N least significant bits of an M-bit digital signal | Dec 28, 1995 | Issued |
Array
(
[id] => 3891847
[patent_doc_number] => 05805483
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[patent_issue_date] => 1998-09-08
[patent_title] => 'Method of converting data outputting sequence in inverse DCT and circuit thereof'
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[pdf_file] => patents/05/805/05805483.pdf
[firstpage_image] =>[orig_patent_app_number] => 581225
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/581225 | Method of converting data outputting sequence in inverse DCT and circuit thereof | Dec 28, 1995 | Issued |
Array
(
[id] => 3891821
[patent_doc_number] => 05805481
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[patent_issue_date] => 1998-09-08
[patent_title] => 'Update block for an adaptive equalizer filter configuration capable of processing complex-valued coefficient signals'
[patent_app_type] => 1
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Array
(
[id] => 3944628
[patent_doc_number] => 05935201
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[patent_title] => 'Multiplier circuit for multiplication operation between binary and twos complement numbers'
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[pdf_file] => patents/05/935/05935201.pdf
[firstpage_image] =>[orig_patent_app_number] => 577305
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/577305 | Multiplier circuit for multiplication operation between binary and twos complement numbers | Dec 21, 1995 | Issued |
Array
(
[id] => 3697086
[patent_doc_number] => 05696711
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[patent_issue_date] => 1997-12-09
[patent_title] => 'Apparatus and method for performing variable precision floating point rounding operations'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/577726 | Apparatus and method for performing variable precision floating point rounding operations | Dec 21, 1995 | Issued |
| 08/575605 | METHOD OF SORTING SIGNED NUMBERS AND SOLVING ABSOLUTE DIFFERENCES USING PACKED INSTRUCTIONS | Dec 19, 1995 | Abandoned |
Array
(
[id] => 4126016
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[patent_title] => 'Method and apparatus for multiplying and accumulating complex numbers in a digital filter'
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[firstpage_image] =>[orig_patent_app_number] => 575778
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/575778 | Method and apparatus for multiplying and accumulating complex numbers in a digital filter | Dec 19, 1995 | Issued |
Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/568096 | Apparatus for inverse discrete cosine transform | Dec 5, 1995 | Issued |
Array
(
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