
Tan V. Mai
Examiner (ID: 15743)
| Most Active Art Unit | 2193 |
| Art Unit(s) | 2306, 2193, 2787, 2786, 2121, 2124, 2302, 2301, 2182, 2183 |
| Total Applications | 3863 |
| Issued Applications | 3431 |
| Pending Applications | 94 |
| Abandoned Applications | 349 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3727395
[patent_doc_number] => 05617344
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-01
[patent_title] => 'Fixed coefficient high decimation filter'
[patent_app_type] => 1
[patent_app_number] => 8/457234
[patent_app_country] => US
[patent_app_date] => 1995-06-01
[patent_effective_date] => 0000-00-00
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[patent_figures_cnt] => 41
[patent_no_of_words] => 14725
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[pdf_file] => patents/05/617/05617344.pdf
[firstpage_image] =>[orig_patent_app_number] => 457234
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/457234 | Fixed coefficient high decimation filter | May 31, 1995 | Issued |
Array
(
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[patent_doc_number] => 05732007
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-24
[patent_title] => 'Computer methods and apparatus for eliminating leading non-significant digits in floating point computations'
[patent_app_type] => 1
[patent_app_number] => 8/457336
[patent_app_country] => US
[patent_app_date] => 1995-06-01
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[pdf_file] => patents/05/732/05732007.pdf
[firstpage_image] =>[orig_patent_app_number] => 457336
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/457336 | Computer methods and apparatus for eliminating leading non-significant digits in floating point computations | May 31, 1995 | Issued |
Array
(
[id] => 3553493
[patent_doc_number] => 05555200
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[patent_kind] => NA
[patent_issue_date] => 1996-09-10
[patent_title] => 'Charge domain bit-serial multiplying digital-analog converter'
[patent_app_type] => 1
[patent_app_number] => 8/457827
[patent_app_country] => US
[patent_app_date] => 1995-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 3549
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[patent_words_short_claim] => 137
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[pdf_file] => patents/05/555/05555200.pdf
[firstpage_image] =>[orig_patent_app_number] => 457827
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/457827 | Charge domain bit-serial multiplying digital-analog converter | May 31, 1995 | Issued |
Array
(
[id] => 3703037
[patent_doc_number] => 05650950
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-22
[patent_title] => 'Apparatus and method for accurately establishing a cut-off frequency in an electronic filter'
[patent_app_type] => 1
[patent_app_number] => 8/455867
[patent_app_country] => US
[patent_app_date] => 1995-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_no_of_words] => 3077
[patent_no_of_claims] => 20
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[pdf_file] => patents/05/650/05650950.pdf
[firstpage_image] =>[orig_patent_app_number] => 455867
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/455867 | Apparatus and method for accurately establishing a cut-off frequency in an electronic filter | May 30, 1995 | Issued |
Array
(
[id] => 3712677
[patent_doc_number] => 05675523
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-07
[patent_title] => 'Waveform data generating apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/453119
[patent_app_country] => US
[patent_app_date] => 1995-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
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[patent_no_of_words] => 8239
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[pdf_file] => patents/05/675/05675523.pdf
[firstpage_image] =>[orig_patent_app_number] => 453119
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/453119 | Waveform data generating apparatus | May 29, 1995 | Issued |
Array
(
[id] => 4411530
[patent_doc_number] => 06298360
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-02
[patent_title] => 'Method and apparatus for generating a highly random number while using existing circuitry'
[patent_app_type] => 1
[patent_app_number] => 8/451796
[patent_app_country] => US
[patent_app_date] => 1995-05-26
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[pdf_file] => patents/06/298/06298360.pdf
[firstpage_image] =>[orig_patent_app_number] => 451796
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/451796 | Method and apparatus for generating a highly random number while using existing circuitry | May 25, 1995 | Issued |
Array
(
[id] => 3638551
[patent_doc_number] => 05687102
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-11
[patent_title] => 'Double precision (64 bit) shift operations using a 32 bit data path'
[patent_app_type] => 1
[patent_app_number] => 8/451195
[patent_app_country] => US
[patent_app_date] => 1995-05-26
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[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/05/687/05687102.pdf
[firstpage_image] =>[orig_patent_app_number] => 451195
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/451195 | Double precision (64 bit) shift operations using a 32 bit data path | May 25, 1995 | Issued |
Array
(
[id] => 3612792
[patent_doc_number] => 05579255
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-26
[patent_title] => 'Analog arithmetic circuit with electric resistor networks and numerical solution method of fourth-order partial differential equation by the use of the circuit'
[patent_app_type] => 1
[patent_app_number] => 8/449487
[patent_app_country] => US
[patent_app_date] => 1995-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/05/579/05579255.pdf
[firstpage_image] =>[orig_patent_app_number] => 449487
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/449487 | Analog arithmetic circuit with electric resistor networks and numerical solution method of fourth-order partial differential equation by the use of the circuit | May 23, 1995 | Issued |
Array
(
[id] => 3835804
[patent_doc_number] => 05732002
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-24
[patent_title] => 'Multi-rate IIR decimation and interpolation filters'
[patent_app_type] => 1
[patent_app_number] => 8/447746
[patent_app_country] => US
[patent_app_date] => 1995-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => patents/05/732/05732002.pdf
[firstpage_image] =>[orig_patent_app_number] => 447746
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/447746 | Multi-rate IIR decimation and interpolation filters | May 22, 1995 | Issued |
Array
(
[id] => 3562411
[patent_doc_number] => 05493525
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-20
[patent_title] => 'Carry-chain compiler'
[patent_app_type] => 1
[patent_app_number] => 8/445505
[patent_app_country] => US
[patent_app_date] => 1995-05-22
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/493/05493525.pdf
[firstpage_image] =>[orig_patent_app_number] => 445505
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/445505 | Carry-chain compiler | May 21, 1995 | Issued |
Array
(
[id] => 3889159
[patent_doc_number] => 05825675
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Apparatus and configuration method for a small, hand-held computing device'
[patent_app_type] => 1
[patent_app_number] => 8/446389
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[patent_app_date] => 1995-05-22
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/446389 | Apparatus and configuration method for a small, hand-held computing device | May 21, 1995 | Issued |
Array
(
[id] => 3632828
[patent_doc_number] => 05612911
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-18
[patent_title] => 'Circuit and method for correction of a linear address during 16-bit addressing'
[patent_app_type] => 1
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[patent_app_date] => 1995-05-18
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[pdf_file] => patents/05/612/05612911.pdf
[firstpage_image] =>[orig_patent_app_number] => 444205
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/444205 | Circuit and method for correction of a linear address during 16-bit addressing | May 17, 1995 | Issued |
Array
(
[id] => 3756426
[patent_doc_number] => 05717617
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-10
[patent_title] => 'Rate change filter and method'
[patent_app_type] => 1
[patent_app_number] => 8/440707
[patent_app_country] => US
[patent_app_date] => 1995-05-15
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[pdf_file] => patents/05/717/05717617.pdf
[firstpage_image] =>[orig_patent_app_number] => 440707
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/440707 | Rate change filter and method | May 14, 1995 | Issued |
Array
(
[id] => 3741051
[patent_doc_number] => 05636154
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-03
[patent_title] => 'Digital operation unit'
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[pdf_file] => patents/05/636/05636154.pdf
[firstpage_image] =>[orig_patent_app_number] => 435315
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/435315 | Digital operation unit | May 4, 1995 | Issued |
Array
(
[id] => 3674103
[patent_doc_number] => 05668749
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-16
[patent_title] => 'Circuit for performing arithmetic operations in a demodulator'
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[firstpage_image] =>[orig_patent_app_number] => 435105
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/435105 | Circuit for performing arithmetic operations in a demodulator | May 3, 1995 | Issued |
Array
(
[id] => 3704907
[patent_doc_number] => 05619440
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[patent_issue_date] => 1997-04-08
[patent_title] => 'Multiplier circuit with rounding-off function'
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[pdf_file] => patents/05/619/05619440.pdf
[firstpage_image] =>[orig_patent_app_number] => 433013
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/433013 | Multiplier circuit with rounding-off function | May 2, 1995 | Issued |
Array
(
[id] => 3598487
[patent_doc_number] => 05517440
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-14
[patent_title] => 'Optimized binary adders and comparators for inputs having different widths'
[patent_app_type] => 1
[patent_app_number] => 8/434162
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[pdf_file] => patents/05/517/05517440.pdf
[firstpage_image] =>[orig_patent_app_number] => 434162
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/434162 | Optimized binary adders and comparators for inputs having different widths | May 1, 1995 | Issued |
| 08/424038 | REDUCED COMPLEXITY MULTIPLE RESONANT TUNNELING CIRCUITS FOR POSITIVE DIGIT MULTIVALUED LOGIC OPERATIONS | Apr 17, 1995 | Abandoned |
Array
(
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Array
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