
Tan V. Mai
Examiner (ID: 15743)
| Most Active Art Unit | 2193 |
| Art Unit(s) | 2306, 2193, 2787, 2786, 2121, 2124, 2302, 2301, 2182, 2183 |
| Total Applications | 3863 |
| Issued Applications | 3431 |
| Pending Applications | 94 |
| Abandoned Applications | 349 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3704069
[patent_doc_number] => 05680340
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[patent_kind] => NA
[patent_issue_date] => 1997-10-21
[patent_title] => 'Low order first bit serial finite field multiplier'
[patent_app_type] => 1
[patent_app_number] => 8/415475
[patent_app_country] => US
[patent_app_date] => 1995-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 133
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[pdf_file] => patents/05/680/05680340.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/415475 | Low order first bit serial finite field multiplier | Mar 30, 1995 | Issued |
Array
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[patent_kind] => NA
[patent_issue_date] => 1998-01-20
[patent_title] => 'Divide to integer'
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[patent_app_number] => 8/414255
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[patent_app_date] => 1995-03-31
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/414255 | Divide to integer | Mar 30, 1995 | Issued |
Array
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[patent_issue_date] => 1997-12-09
[patent_title] => 'Program controlled rounding modes'
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[patent_app_number] => 8/414866
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[patent_app_date] => 1995-03-31
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[patent_drawing_sheets_cnt] => 3
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Array
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[patent_issue_date] => 1998-05-26
[patent_title] => 'Parallel calculation of exponent and sticky bit during normalization'
[patent_app_type] => 1
[patent_app_number] => 8/414072
[patent_app_country] => US
[patent_app_date] => 1995-03-31
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[firstpage_image] =>[orig_patent_app_number] => 414072
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/414072 | Parallel calculation of exponent and sticky bit during normalization | Mar 30, 1995 | Issued |
Array
(
[id] => 3697045
[patent_doc_number] => 05696708
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[patent_kind] => NA
[patent_issue_date] => 1997-12-09
[patent_title] => 'Digital filter with decimated frequency response'
[patent_app_type] => 1
[patent_app_number] => 8/413356
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[patent_app_date] => 1995-03-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/413356 | Digital filter with decimated frequency response | Mar 29, 1995 | Issued |
Array
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[patent_doc_number] => 05717621
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[patent_issue_date] => 1998-02-10
[patent_title] => 'Speedup for solution of systems of linear equations'
[patent_app_type] => 1
[patent_app_number] => 8/411918
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 411918
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/411918 | Speedup for solution of systems of linear equations | Mar 27, 1995 | Issued |
Array
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[patent_doc_number] => 05629881
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[patent_kind] => NA
[patent_issue_date] => 1997-05-13
[patent_title] => 'Method for filtering a digital value train with improved noise behavior, and circuit configuration for performing the method'
[patent_app_type] => 1
[patent_app_number] => 8/404366
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[pdf_file] => patents/05/629/05629881.pdf
[firstpage_image] =>[orig_patent_app_number] => 404366
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/404366 | Method for filtering a digital value train with improved noise behavior, and circuit configuration for performing the method | Mar 14, 1995 | Issued |
Array
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[id] => 3617747
[patent_doc_number] => 05590067
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[patent_issue_date] => 1996-12-31
[patent_title] => 'Method and arrangement for transformation of signals from a frequency to a time domain'
[patent_app_type] => 1
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[pdf_file] => patents/05/590/05590067.pdf
[firstpage_image] =>[orig_patent_app_number] => 404067
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/404067 | Method and arrangement for transformation of signals from a frequency to a time domain | Mar 13, 1995 | Issued |
Array
(
[id] => 3500769
[patent_doc_number] => 05561617
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-01
[patent_title] => 'Pyramid processor integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/402402
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 402402
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/402402 | Pyramid processor integrated circuit | Mar 9, 1995 | Issued |
Array
(
[id] => 3901816
[patent_doc_number] => RE036388
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[patent_issue_date] => 1999-11-09
[patent_title] => 'Sine/cosine generator and method'
[patent_app_type] => 2
[patent_app_number] => 8/400811
[patent_app_country] => US
[patent_app_date] => 1995-03-08
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[pdf_file] => patents/RE/036/RE036388.pdf
[firstpage_image] =>[orig_patent_app_number] => 400811
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/400811 | Sine/cosine generator and method | Mar 7, 1995 | Issued |
Array
(
[id] => 3632783
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[patent_title] => 'Method and arrangement for transformation of signals from a frequency to a time domain'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/400723 | Method and arrangement for transformation of signals from a frequency to a time domain | Mar 6, 1995 | Issued |
Array
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Array
(
[id] => 3562991
[patent_doc_number] => 05574678
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[patent_issue_date] => 1996-11-12
[patent_title] => 'Continuous time programmable analog block architecture'
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[patent_app_number] => 8/396994
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[firstpage_image] =>[orig_patent_app_number] => 396994
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/396994 | Continuous time programmable analog block architecture | Feb 28, 1995 | Issued |
Array
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[id] => 4010407
[patent_doc_number] => 05923579
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[patent_title] => 'Optimized binary adder and comparator having an implicit constant for an input'
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[pdf_file] => patents/05/923/05923579.pdf
[firstpage_image] =>[orig_patent_app_number] => 393619
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/393619 | Optimized binary adder and comparator having an implicit constant for an input | Feb 21, 1995 | Issued |
Array
(
[id] => 3596424
[patent_doc_number] => 05553011
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[patent_issue_date] => 1996-09-03
[patent_title] => 'Waveform generating apparatus for musical instrument'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/391466 | Waveform generating apparatus for musical instrument | Feb 20, 1995 | Issued |
Array
(
[id] => 3515345
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[patent_title] => 'Processing system and method for minimum/maximum number determination'
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[firstpage_image] =>[orig_patent_app_number] => 388324
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/388324 | Processing system and method for minimum/maximum number determination | Feb 13, 1995 | Issued |
| 08/389064 | DIGITAL SIGNAL PROCESSING | Feb 13, 1995 | Abandoned |
Array
(
[id] => 3623163
[patent_doc_number] => 05535150
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[patent_issue_date] => 1996-07-09
[patent_title] => 'Single chip adaptive filter utilizing updatable weighting techniques'
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[patent_app_number] => 8/388170
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 388170
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/388170 | Single chip adaptive filter utilizing updatable weighting techniques | Feb 9, 1995 | Issued |
| 08/386254 | LOGIC STRUCTURE AND CIRCUIT FOR FAST CARRY | Feb 8, 1995 | Abandoned |
Array
(
[id] => 3783616
[patent_doc_number] => 05774383
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