Search

Tan V. Mai

Examiner (ID: 15743)

Most Active Art Unit
2193
Art Unit(s)
2306, 2193, 2787, 2786, 2121, 2124, 2302, 2301, 2182, 2183
Total Applications
3863
Issued Applications
3431
Pending Applications
94
Abandoned Applications
349

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3740768 [patent_doc_number] => 05666300 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Power reduction in a data processing system using pipeline registers and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/361405 [patent_app_country] => US [patent_app_date] => 1994-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4620 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/666/05666300.pdf [firstpage_image] =>[orig_patent_app_number] => 361405 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/361405
Power reduction in a data processing system using pipeline registers and method therefor Dec 21, 1994 Issued
Array ( [id] => 3657646 [patent_doc_number] => 05638308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-10 [patent_title] => 'Calculator with keys which can selectively be disabled' [patent_app_type] => 1 [patent_app_number] => 8/361815 [patent_app_country] => US [patent_app_date] => 1994-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3022 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/638/05638308.pdf [firstpage_image] =>[orig_patent_app_number] => 361815 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/361815
Calculator with keys which can selectively be disabled Dec 21, 1994 Issued
Array ( [id] => 3673873 [patent_doc_number] => 05598362 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Apparatus and method for performing both 24 bit and 16 bit arithmetic' [patent_app_type] => 1 [patent_app_number] => 8/361406 [patent_app_country] => US [patent_app_date] => 1994-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4631 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/598/05598362.pdf [firstpage_image] =>[orig_patent_app_number] => 361406 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/361406
Apparatus and method for performing both 24 bit and 16 bit arithmetic Dec 21, 1994 Issued
08/362296 PIPELINED ALIGNMENT SHIFTER AND METHOD FOR UNIVERSAL BIT FIELD BOUNDARY ALIGNMENT Dec 21, 1994 Abandoned
Array ( [id] => 3520775 [patent_doc_number] => 05563819 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-08 [patent_title] => 'Fast high precision discrete-time analog finite impulse response filter' [patent_app_type] => 1 [patent_app_number] => 8/360539 [patent_app_country] => US [patent_app_date] => 1994-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 6978 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/563/05563819.pdf [firstpage_image] =>[orig_patent_app_number] => 360539 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/360539
Fast high precision discrete-time analog finite impulse response filter Dec 20, 1994 Issued
Array ( [id] => 3712354 [patent_doc_number] => 05646874 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-08 [patent_title] => 'Multiplication/multiplication-accumulation method and computing device' [patent_app_type] => 1 [patent_app_number] => 8/363064 [patent_app_country] => US [patent_app_date] => 1994-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2505 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/646/05646874.pdf [firstpage_image] =>[orig_patent_app_number] => 363064 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/363064
Multiplication/multiplication-accumulation method and computing device Dec 20, 1994 Issued
Array ( [id] => 3516362 [patent_doc_number] => 05570308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-29 [patent_title] => 'Method of processing digital audio signals of different sampling rates' [patent_app_type] => 1 [patent_app_number] => 8/360016 [patent_app_country] => US [patent_app_date] => 1994-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6869 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/570/05570308.pdf [firstpage_image] =>[orig_patent_app_number] => 360016 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/360016
Method of processing digital audio signals of different sampling rates Dec 19, 1994 Issued
Array ( [id] => 3437981 [patent_doc_number] => 05463571 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-31 [patent_title] => 'Multi-nary OR logic device' [patent_app_type] => 1 [patent_app_number] => 8/357245 [patent_app_country] => US [patent_app_date] => 1994-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2361 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/463/05463571.pdf [firstpage_image] =>[orig_patent_app_number] => 357245 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/357245
Multi-nary OR logic device Dec 12, 1994 Issued
Array ( [id] => 3437996 [patent_doc_number] => 05463572 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-31 [patent_title] => 'Multi-nary and logic device' [patent_app_type] => 1 [patent_app_number] => 8/357246 [patent_app_country] => US [patent_app_date] => 1994-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2360 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/463/05463572.pdf [firstpage_image] =>[orig_patent_app_number] => 357246 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/357246
Multi-nary and logic device Dec 12, 1994 Issued
Array ( [id] => 3546681 [patent_doc_number] => 05495433 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-27 [patent_title] => 'Data processing circuit' [patent_app_type] => 1 [patent_app_number] => 8/353163 [patent_app_country] => US [patent_app_date] => 1994-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4835 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/495/05495433.pdf [firstpage_image] =>[orig_patent_app_number] => 353163 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/353163
Data processing circuit Dec 8, 1994 Issued
Array ( [id] => 3560539 [patent_doc_number] => 05572454 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'Modulo reduction method using a precomputed table' [patent_app_type] => 1 [patent_app_number] => 8/353266 [patent_app_country] => US [patent_app_date] => 1994-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3407 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/572/05572454.pdf [firstpage_image] =>[orig_patent_app_number] => 353266 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/353266
Modulo reduction method using a precomputed table Dec 4, 1994 Issued
Array ( [id] => 3601157 [patent_doc_number] => 05568413 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-22 [patent_title] => 'Analog circuit implementing fuzzy rules with polynomial output coefficients' [patent_app_type] => 1 [patent_app_number] => 8/352082 [patent_app_country] => US [patent_app_date] => 1994-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3082 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/568/05568413.pdf [firstpage_image] =>[orig_patent_app_number] => 352082 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/352082
Analog circuit implementing fuzzy rules with polynomial output coefficients Nov 29, 1994 Issued
Array ( [id] => 3526747 [patent_doc_number] => 05576984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-19 [patent_title] => 'Hydrodynamic bearing rotor orbit simulator' [patent_app_type] => 1 [patent_app_number] => 8/346703 [patent_app_country] => US [patent_app_date] => 1994-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 2918 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/576/05576984.pdf [firstpage_image] =>[orig_patent_app_number] => 346703 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/346703
Hydrodynamic bearing rotor orbit simulator Nov 29, 1994 Issued
Array ( [id] => 3544596 [patent_doc_number] => 05557561 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-17 [patent_title] => 'Multiple signal, digital differential signal processor and interpolator' [patent_app_type] => 1 [patent_app_number] => 8/342882 [patent_app_country] => US [patent_app_date] => 1994-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2757 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/557/05557561.pdf [firstpage_image] =>[orig_patent_app_number] => 342882 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/342882
Multiple signal, digital differential signal processor and interpolator Nov 20, 1994 Issued
Array ( [id] => 3529767 [patent_doc_number] => 05530663 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Floating point unit for calculating a compound instruction A+B.times.C in two cycles' [patent_app_type] => 1 [patent_app_number] => 8/339115 [patent_app_country] => US [patent_app_date] => 1994-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4678 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530663.pdf [firstpage_image] =>[orig_patent_app_number] => 339115 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/339115
Floating point unit for calculating a compound instruction A+B.times.C in two cycles Nov 13, 1994 Issued
Array ( [id] => 3656983 [patent_doc_number] => 05629885 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Squaring circuit for binary numbers' [patent_app_type] => 1 [patent_app_number] => 8/335576 [patent_app_country] => US [patent_app_date] => 1994-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 5672 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/629/05629885.pdf [firstpage_image] =>[orig_patent_app_number] => 335576 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/335576
Squaring circuit for binary numbers Nov 6, 1994 Issued
Array ( [id] => 3565698 [patent_doc_number] => 05544084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-06 [patent_title] => 'Multiplier composed of integrated semiconductor circuit occupying reduced area' [patent_app_type] => 1 [patent_app_number] => 8/335964 [patent_app_country] => US [patent_app_date] => 1994-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3066 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/544/05544084.pdf [firstpage_image] =>[orig_patent_app_number] => 335964 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/335964
Multiplier composed of integrated semiconductor circuit occupying reduced area Nov 6, 1994 Issued
Array ( [id] => 3596503 [patent_doc_number] => 05553014 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-03 [patent_title] => 'Adaptive finite impulse response filtering method and apparatus' [patent_app_type] => 1 [patent_app_number] => 8/332224 [patent_app_country] => US [patent_app_date] => 1994-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7735 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/553/05553014.pdf [firstpage_image] =>[orig_patent_app_number] => 332224 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/332224
Adaptive finite impulse response filtering method and apparatus Oct 30, 1994 Issued
Array ( [id] => 3630921 [patent_doc_number] => 05689452 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'Method and apparatus for performing arithmetic in large galois field GF(2.sup.n)' [patent_app_type] => 1 [patent_app_number] => 8/332235 [patent_app_country] => US [patent_app_date] => 1994-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 7539 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/689/05689452.pdf [firstpage_image] =>[orig_patent_app_number] => 332235 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/332235
Method and apparatus for performing arithmetic in large galois field GF(2.sup.n) Oct 30, 1994 Issued
Array ( [id] => 3841166 [patent_doc_number] => 05712809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Method and apparatus for performing fast reduced coefficient discrete cosine transforms' [patent_app_type] => 1 [patent_app_number] => 8/332535 [patent_app_country] => US [patent_app_date] => 1994-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4753 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/712/05712809.pdf [firstpage_image] =>[orig_patent_app_number] => 332535 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/332535
Method and apparatus for performing fast reduced coefficient discrete cosine transforms Oct 30, 1994 Issued
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