Search

Tan V. Mai

Examiner (ID: 9332, Phone: (571)272-3726 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2121, 2301, 2124, 2182, 2183, 2786, 2306, 2787, 2193, 2302
Total Applications
3863
Issued Applications
3434
Pending Applications
94
Abandoned Applications
349

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16307657 [patent_doc_number] => 10776451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Configurable FFT architecture [patent_app_type] => utility [patent_app_number] => 16/669277 [patent_app_country] => US [patent_app_date] => 2019-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7497 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16669277 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/669277
Configurable FFT architecture Oct 29, 2019 Issued
Array ( [id] => 18415204 [patent_doc_number] => 11669747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Constraining function approximation hardware integrated with fixed-point to floating-point conversion [patent_app_type] => utility [patent_app_number] => 16/667821 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 11111 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667821 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667821
Constraining function approximation hardware integrated with fixed-point to floating-point conversion Oct 28, 2019 Issued
Array ( [id] => 15772423 [patent_doc_number] => 20200117229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => Variable Phase and Frequency Pulse-Width Modulation Technique [patent_app_type] => utility [patent_app_number] => 16/600496 [patent_app_country] => US [patent_app_date] => 2019-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16600496 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/600496
Variable phase and frequency pulse-width modulation technique Oct 11, 2019 Issued
Array ( [id] => 17288190 [patent_doc_number] => 11204739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-21 [patent_title] => Microcontroller for executing a configurable processing operation [patent_app_type] => utility [patent_app_number] => 16/599581 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3836 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16599581 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/599581
Microcontroller for executing a configurable processing operation Oct 10, 2019 Issued
Array ( [id] => 16751420 [patent_doc_number] => 20210103429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => FLOATING POINT MULTIPLY HARDWARE USING DECOMPOSED COMPONENT NUMBERS [patent_app_type] => utility [patent_app_number] => 16/591042 [patent_app_country] => US [patent_app_date] => 2019-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16591042 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/591042
Floating point multiply hardware using decomposed component numbers Oct 1, 2019 Issued
Array ( [id] => 18934105 [patent_doc_number] => 11886534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Filtering method and system of parallel computing results [patent_app_type] => utility [patent_app_number] => 17/615582 [patent_app_country] => US [patent_app_date] => 2019-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5492 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17615582 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/615582
Filtering method and system of parallel computing results Sep 28, 2019 Issued
Array ( [id] => 15412343 [patent_doc_number] => 20200026494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => MACHINE LEARNING TRAINING ARCHITECTURE FOR PROGRAMMABLE DEVICES [patent_app_type] => utility [patent_app_number] => 16/585857 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16585857 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/585857
Machine learning training architecture for programmable devices Sep 26, 2019 Issued
Array ( [id] => 17091911 [patent_doc_number] => 11120101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Matrix multiplication system and method [patent_app_type] => utility [patent_app_number] => 16/585265 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12927 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16585265 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/585265
Matrix multiplication system and method Sep 26, 2019 Issued
Array ( [id] => 16248484 [patent_doc_number] => 10747846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Efficient matrix property determination with pipelining and parallelism [patent_app_type] => utility [patent_app_number] => 16/582916 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 31 [patent_no_of_words] => 10374 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582916 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/582916
Efficient matrix property determination with pipelining and parallelism Sep 24, 2019 Issued
Array ( [id] => 15689455 [patent_doc_number] => 20200099391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => METHOD FOR COMPRESSING A QUANTUM STATE VECTOR AND PROCESS FOR STORING A QUANTUM STATE VECTOR [patent_app_type] => utility [patent_app_number] => 16/578736 [patent_app_country] => US [patent_app_date] => 2019-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16578736 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/578736
Method for compressing a quantum state vector and process for storing a quantum state vector Sep 22, 2019 Issued
Array ( [id] => 17878364 [patent_doc_number] => 11450385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Digital RRAM-based convolutional block [patent_app_type] => utility [patent_app_number] => 16/577309 [patent_app_country] => US [patent_app_date] => 2019-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 5757 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16577309 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/577309
Digital RRAM-based convolutional block Sep 19, 2019 Issued
Array ( [id] => 16676190 [patent_doc_number] => 20210064956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => CLASSIFYING BUSINESS SUMMARIES AGAINST A HIERARCHICAL INDUSTRY CLASSIFICATION STRUCTURE USING SUPERVISED MACHINE LEARNING [patent_app_type] => utility [patent_app_number] => 16/559963 [patent_app_country] => US [patent_app_date] => 2019-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16559963 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/559963
Classifying business summaries against a hierarchical industry classification structure using supervised machine learning Sep 3, 2019 Issued
Array ( [id] => 16675614 [patent_doc_number] => 20210064380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => Digital Filter with Programmable Impulse Response for Direct Amplitude Modulation at Radio Frequency [patent_app_type] => utility [patent_app_number] => 16/557357 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5928 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16557357 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/557357
Digital filter with programmable impulse response for direct amplitude modulation at radio frequency Aug 29, 2019 Issued
Array ( [id] => 17955363 [patent_doc_number] => 11481471 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Mapping convolution to a matrix processor unit [patent_app_type] => utility [patent_app_number] => 16/543241 [patent_app_country] => US [patent_app_date] => 2019-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 15747 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16543241 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/543241
Mapping convolution to a matrix processor unit Aug 15, 2019 Issued
Array ( [id] => 16630578 [patent_doc_number] => 20210049231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => Multiple Output Fusion For Operations Performed In A Multi-Dimensional Array of Processing Units [patent_app_type] => utility [patent_app_number] => 16/543282 [patent_app_country] => US [patent_app_date] => 2019-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11618 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16543282 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/543282
Multiple output fusion for operations performed in a multi-dimensional array of processing units Aug 15, 2019 Issued
Array ( [id] => 15501543 [patent_doc_number] => 20200050960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => METHOD OF MODELING INTERACTIONS BETWEEN MANY PARTICLES [patent_app_type] => utility [patent_app_number] => 16/539995 [patent_app_country] => US [patent_app_date] => 2019-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8370 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16539995 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/539995
Method of modeling interactions between many particles Aug 12, 2019 Issued
Array ( [id] => 17110451 [patent_doc_number] => 20210291048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => MULTI-PROCESS INTERFACE CONTROLLER [patent_app_type] => utility [patent_app_number] => 17/266237 [patent_app_country] => US [patent_app_date] => 2019-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10418 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17266237 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/266237
MULTI-PROCESS INTERFACE CONTROLLER Aug 8, 2019 Abandoned
Array ( [id] => 19413546 [patent_doc_number] => 12079363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Secure joining information generation system, secure joining system, methods therefor, secure computing apparatus and program [patent_app_type] => utility [patent_app_number] => 17/267808 [patent_app_country] => US [patent_app_date] => 2019-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 10358 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 613 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17267808 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/267808
Secure joining information generation system, secure joining system, methods therefor, secure computing apparatus and program Aug 7, 2019 Issued
Array ( [id] => 15152185 [patent_doc_number] => 20190354570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => PERMUTING IN A MATRIX-VECTOR PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/528826 [patent_app_country] => US [patent_app_date] => 2019-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16528826 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/528826
Permuting in a matrix-vector processor Jul 31, 2019 Issued
Array ( [id] => 16895274 [patent_doc_number] => 11036828 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-15 [patent_title] => Identifying checksum mechanisms using linear equations [patent_app_type] => utility [patent_app_number] => 16/526863 [patent_app_country] => US [patent_app_date] => 2019-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16526863 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/526863
Identifying checksum mechanisms using linear equations Jul 29, 2019 Issued
Menu