Tan V. Mai

Array ( [id] => 3452172 [patent_doc_number] => 05467299 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-14 [patent_title] => 'Divider and microcomputer including the same' [patent_app_type] => 1 [patent_app_number] => 8/206585 [patent_app_country] => US [patent_app_date] => 1994-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 10938 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/467/05467299.pdf [firstpage_image] =>[orig_patent_app_number] => 206585 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3451336 [patent_doc_number] => 05430668 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Floating point multiplier capable of easily performing a failure detection test' [patent_app_type] => 1 [patent_app_number] => 8/206834 [patent_app_country] => US [patent_app_date] => 1994-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2971 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/430/05430668.pdf [firstpage_image] =>[orig_patent_app_number] => 206834 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3469258 [patent_doc_number] => 05442582 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-15 [patent_title] => 'Transversal filter allrate equalizer for use at intermediate frequency' [patent_app_type] => 1 [patent_app_number] => 8/206065 [patent_app_country] => US [patent_app_date] => 1994-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2482 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/442/05442582.pdf [firstpage_image] =>[orig_patent_app_number] => 206065 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3565796 [patent_doc_number] => 05544091 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-06 [patent_title] => 'Circuit scale reduction for bit-serial digital signal processing' [patent_app_type] => 1 [patent_app_number] => 8/205844 [patent_app_country] => US [patent_app_date] => 1994-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 69 [patent_no_of_words] => 21869 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/544/05544091.pdf [firstpage_image] =>[orig_patent_app_number] => 205844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3463959 [patent_doc_number] => 05452242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-19 [patent_title] => 'Method and apparatus for multiplying a plurality of numbers' [patent_app_type] => 1 [patent_app_number] => 8/204004 [patent_app_country] => US [patent_app_date] => 1994-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 14843 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 450 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/452/05452242.pdf [firstpage_image] =>[orig_patent_app_number] => 204004 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3421954 [patent_doc_number] => 05444646 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-22 [patent_title] => 'Fully static 32 bit alu with two stage carry bypass' [patent_app_type] => 1 [patent_app_number] => 8/204750 [patent_app_country] => US [patent_app_date] => 1994-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 7343 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/444/05444646.pdf [firstpage_image] =>[orig_patent_app_number] => 204750 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3130638 [patent_doc_number] => 05384723 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-24 [patent_title] => 'Method and apparatus for floating point normalization' [patent_app_type] => 1 [patent_app_number] => 8/205123 [patent_app_country] => US [patent_app_date] => 1994-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5182 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/384/05384723.pdf [firstpage_image] =>[orig_patent_app_number] => 205123 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3495016 [patent_doc_number] => 05426598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-20 [patent_title] => 'Adder and multiplier circuit employing the same' [patent_app_type] => 1 [patent_app_number] => 8/199655 [patent_app_country] => US [patent_app_date] => 1994-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4006 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/426/05426598.pdf [firstpage_image] =>[orig_patent_app_number] => 199655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3527034 [patent_doc_number] => 05506801 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-09 [patent_title] => 'High-performance ultra-low power VLSI analog processor for data compression' [patent_app_type] => 1 [patent_app_number] => 8/196295 [patent_app_country] => US [patent_app_date] => 1994-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5526 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/506/05506801.pdf [firstpage_image] =>[orig_patent_app_number] => 196295 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3118292 [patent_doc_number] => 05408427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-18 [patent_title] => 'Detection of exponent underflow and overflow in a floating point adder' [patent_app_type] => 1 [patent_app_number] => 8/194534 [patent_app_country] => US [patent_app_date] => 1994-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6186 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 497 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/408/05408427.pdf [firstpage_image] =>[orig_patent_app_number] => 194534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3632786 [patent_doc_number] => 05612908 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'Processing element for parallel array processor' [patent_app_type] => 1 [patent_app_number] => 8/194364 [patent_app_country] => US [patent_app_date] => 1994-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 41 [patent_no_of_words] => 8290 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/612/05612908.pdf [firstpage_image] =>[orig_patent_app_number] => 194364 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3497414 [patent_doc_number] => 05475627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-12 [patent_title] => 'Digital wave synthesizer with address conversion for reducing memory capacity' [patent_app_type] => 1 [patent_app_number] => 8/190844 [patent_app_country] => US [patent_app_date] => 1994-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2473 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/475/05475627.pdf [firstpage_image] =>[orig_patent_app_number] => 190844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3791794 [patent_doc_number] => 05818744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Circuit and method for determining multiplicative inverses with a look-up table' [patent_app_type] => 1 [patent_app_number] => 8/191564 [patent_app_country] => US [patent_app_date] => 1994-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4453 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818744.pdf [firstpage_image] =>[orig_patent_app_number] => 191564 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3467155 [patent_doc_number] => 05473554 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-05 [patent_title] => 'CMOS multiplexor' [patent_app_type] => 1 [patent_app_number] => 8/190253 [patent_app_country] => US [patent_app_date] => 1994-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 7253 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/473/05473554.pdf [firstpage_image] =>[orig_patent_app_number] => 190253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3632978 [patent_doc_number] => 05602766 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Method of and device for forming the sum of a chain of products' [patent_app_type] => 1 [patent_app_number] => 8/190068 [patent_app_country] => US [patent_app_date] => 1994-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 2853 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/602/05602766.pdf [firstpage_image] =>[orig_patent_app_number] => 190068 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3549463 [patent_doc_number] => 05481487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-02 [patent_title] => 'Transpose memory for DCT/IDCT circuit' [patent_app_type] => 1 [patent_app_number] => 8/189446 [patent_app_country] => US [patent_app_date] => 1994-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 12995 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/481/05481487.pdf [firstpage_image] =>[orig_patent_app_number] => 189446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3574141 [patent_doc_number] => 05483476 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-09 [patent_title] => 'Mantissa addition system for a floating point adder' [patent_app_type] => 1 [patent_app_number] => 8/186724 [patent_app_country] => US [patent_app_date] => 1994-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4547 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/483/05483476.pdf [firstpage_image] =>[orig_patent_app_number] => 186724 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3120380 [patent_doc_number] => 05465225 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-07 [patent_title] => 'Method of increasing the data-processing speed of a signal processor' [patent_app_type] => 1 [patent_app_number] => 8/185626 [patent_app_country] => US [patent_app_date] => 1994-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2345 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/465/05465225.pdf [firstpage_image] =>[orig_patent_app_number] => 185626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3455362 [patent_doc_number] => 05420806 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-30 [patent_title] => 'Multiplication circuit for multiplying analog signals by digital signals' [patent_app_type] => 1 [patent_app_number] => 8/181118 [patent_app_country] => US [patent_app_date] => 1994-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1232 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/420/05420806.pdf [firstpage_image] =>[orig_patent_app_number] => 181118 [rel_patent_id] =>[rel_patent_doc_number] =>)