Tan V Mai

Array ( [id] => 16217120 [patent_doc_number] => 10732932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Methods for using a multiplier circuit to support multiple sub-multiplications using bit correction and extension [patent_app_type] => utility [patent_app_number] => 16/231170 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 10373 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16231170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14218905 [patent_doc_number] => 20190121837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => APPARATUS AND METHOD FOR A MASKED MULTIPLY INSTRUCTION TO SUPPORT NEURAL NETWORK PRUNING OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/230814 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17921 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16230814 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16574122 [patent_doc_number] => 10896045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-19 [patent_title] => Architecture for dense operations in machine learning inference engine [patent_app_type] => utility [patent_app_number] => 16/226550 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12784 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16560063 [patent_doc_number] => 20210005212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => METHODS AND APPARATUS SYSTEMS FOR UNIFIED SPEECH AND AUDIO DECODING IMPROVEMENTS [patent_app_type] => utility [patent_app_number] => 16/955075 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30481 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16955075 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16232880 [patent_doc_number] => 10740432 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-11 [patent_title] => Hardware implementation of mathematical functions [patent_app_type] => utility [patent_app_number] => 16/219604 [patent_app_country] => US [patent_app_date] => 2018-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13097 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16219604 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16463018 [patent_doc_number] => 10846366 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-24 [patent_title] => Selecting parameters for a quantum approximate optimization algorithm (QAOA) [patent_app_type] => utility [patent_app_number] => 16/217410 [patent_app_country] => US [patent_app_date] => 2018-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 7665 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16217410 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16615678 [patent_doc_number] => 20210034331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => PRODUCT-SUM OPERATION DEVICE, NEUROMORPHIC DEVICE, AND METHOD FOR DETERMINING MALFUNCTION IN PRODUCT-SUM OPERATION DEVICE [patent_app_type] => utility [patent_app_number] => 16/766426 [patent_app_country] => US [patent_app_date] => 2018-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9566 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16766426 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16520914 [patent_doc_number] => 10872129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-22 [patent_title] => Methods for providing automated scalable strategic modelling and devices thereof [patent_app_type] => utility [patent_app_number] => 16/216610 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7429 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16216610 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16565742 [patent_doc_number] => 10891110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => AES/CRC engine based on resource shared galois field computation [patent_app_type] => utility [patent_app_number] => 16/215587 [patent_app_country] => US [patent_app_date] => 2018-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7436 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16215587 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16217681 [patent_doc_number] => 10733498 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-04 [patent_title] => Parametric mathematical function approximation in integrated circuits [patent_app_type] => utility [patent_app_number] => 16/215405 [patent_app_country] => US [patent_app_date] => 2018-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11991 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16215405 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14162181 [patent_doc_number] => 20190108193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => RESISTIVE MEMORY ARRAYS FOR PERFORMING MULTIPLY-ACCUMULATE OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/213385 [patent_app_country] => US [patent_app_date] => 2018-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8214 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16213385 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17288565 [patent_doc_number] => 11205115 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-12-21 [patent_title] => Neural network inference circuit [patent_app_type] => utility [patent_app_number] => 16/212622 [patent_app_country] => US [patent_app_date] => 2018-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 20456 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16212622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17516044 [patent_doc_number] => 11295200 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-05 [patent_title] => Time-multiplexed dot products for neural network inference circuit [patent_app_type] => utility [patent_app_number] => 16/212646 [patent_app_country] => US [patent_app_date] => 2018-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 32859 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16212646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16067137 [patent_doc_number] => 10692527 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-23 [patent_title] => Target parameter adaptation [patent_app_type] => utility [patent_app_number] => 16/211186 [patent_app_country] => US [patent_app_date] => 2018-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3710 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16211186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16234627 [patent_doc_number] => 10742196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => Apparatus and method for performing digital infinite impulse filtering [patent_app_type] => utility [patent_app_number] => 16/207061 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5108 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16207061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16522105 [patent_doc_number] => 10873332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-22 [patent_title] => Adder circuitry for very large integers [patent_app_type] => utility [patent_app_number] => 16/206748 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 8832 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16206748 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16145455 [patent_doc_number] => 10705797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Parallel-prefix adder and method [patent_app_type] => utility [patent_app_number] => 16/200689 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 11399 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16200689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15982121 [patent_doc_number] => 10671388 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-02 [patent_title] => Vectorization of wide integer data paths for parallel operations with side-band logic monitoring the numeric overflow between vector lanes [patent_app_type] => utility [patent_app_number] => 16/200313 [patent_app_country] => US [patent_app_date] => 2018-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8985 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16200313 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16607875 [patent_doc_number] => 10908878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Dynamic directional rounding [patent_app_type] => utility [patent_app_number] => 16/200325 [patent_app_country] => US [patent_app_date] => 2018-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 11718 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16200325 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15936355 [patent_doc_number] => 20200159811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => ASSIGNING DEPENDENT MATRIX-VECTOR MULTIPLICATION OPERATIONS TO CONSECUTIVE CROSSBARS OF A DOT PRODUCT ENGINE [patent_app_type] => utility [patent_app_number] => 16/196423 [patent_app_country] => US [patent_app_date] => 2018-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16196423 [rel_patent_id] =>[rel_patent_doc_number] =>)