
Tan V Mai
Examiner (ID: 13419, Phone: (571)272-3726 , Office: P/2182 )
| Most Active Art Unit | 2193 |
| Art Unit(s) | 2787, 2183, 2121, 2182, 2193, 2301, 2306, 2124, 2786, 2302 |
| Total Applications | 3863 |
| Issued Applications | 3431 |
| Pending Applications | 94 |
| Abandoned Applications | 349 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 14235493
[patent_doc_number] => 20190129919
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-02
[patent_title] => ANALYTIC SYSTEM FOR FAST QUANTILE COMPUTATION WITH IMPROVED MEMORY CONSUMPTION STRATEGY
[patent_app_type] => utility
[patent_app_number] => 16/140931
[patent_app_country] => US
[patent_app_date] => 2018-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14530
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -27
[patent_words_short_claim] => 455
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16140931
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/140931 | Analytic system for fast quantile computation with improved memory consumption strategy | Sep 24, 2018 | Issued |
Array
(
[id] => 16323250
[patent_doc_number] => 10783216
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-22
[patent_title] => Methods and apparatus for in-place fast Fourier transform
[patent_app_type] => utility
[patent_app_number] => 16/139339
[patent_app_country] => US
[patent_app_date] => 2018-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 5942
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16139339
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/139339 | Methods and apparatus for in-place fast Fourier transform | Sep 23, 2018 | Issued |
Array
(
[id] => 16307287
[patent_doc_number] => 10776078
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-09-15
[patent_title] => Multimodal multiplier systems and methods
[patent_app_type] => utility
[patent_app_number] => 16/139093
[patent_app_country] => US
[patent_app_date] => 2018-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6190
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 276
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16139093
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/139093 | Multimodal multiplier systems and methods | Sep 22, 2018 | Issued |
Array
(
[id] => 16200578
[patent_doc_number] => 10725741
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-28
[patent_title] => Digital circuit with compressed carry
[patent_app_type] => utility
[patent_app_number] => 16/138726
[patent_app_country] => US
[patent_app_date] => 2018-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4730
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16138726
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/138726 | Digital circuit with compressed carry | Sep 20, 2018 | Issued |
Array
(
[id] => 16248143
[patent_doc_number] => 10747502
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-08-18
[patent_title] => Multiply and accumulate circuit
[patent_app_type] => utility
[patent_app_number] => 16/136041
[patent_app_country] => US
[patent_app_date] => 2018-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5753
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16136041
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/136041 | Multiply and accumulate circuit | Sep 18, 2018 | Issued |
Array
(
[id] => 15297769
[patent_doc_number] => 20190392020
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-26
[patent_title] => RECONFIGURABLE CONVOLUTION ACCELERATOR
[patent_app_type] => utility
[patent_app_number] => 16/135947
[patent_app_country] => US
[patent_app_date] => 2018-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5359
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16135947
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/135947 | Reconfigurable convolution accelerator | Sep 18, 2018 | Issued |
Array
(
[id] => 17031768
[patent_doc_number] => 11093582
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-17
[patent_title] => Method for calculating axis deviation of rotor assembly based on end face runout measurement
[patent_app_type] => utility
[patent_app_number] => 16/652838
[patent_app_country] => US
[patent_app_date] => 2018-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2709
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 1614
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16652838
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/652838 | Method for calculating axis deviation of rotor assembly based on end face runout measurement | Sep 11, 2018 | Issued |
Array
(
[id] => 16408751
[patent_doc_number] => 10817304
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-10-27
[patent_title] => Calculating device
[patent_app_type] => utility
[patent_app_number] => 16/118646
[patent_app_country] => US
[patent_app_date] => 2018-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 43
[patent_no_of_words] => 15723
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16118646
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/118646 | Calculating device | Aug 30, 2018 | Issued |
Array
(
[id] => 15472493
[patent_doc_number] => 10552120
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-02-04
[patent_title] => Systems and methods for single chip quantum random number generation
[patent_app_type] => utility
[patent_app_number] => 16/105793
[patent_app_country] => US
[patent_app_date] => 2018-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 30680
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16105793
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/105793 | Systems and methods for single chip quantum random number generation | Aug 19, 2018 | Issued |
Array
(
[id] => 14523877
[patent_doc_number] => 10339201
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-07-02
[patent_title] => Dot product based processing elements
[patent_app_type] => utility
[patent_app_number] => 16/102431
[patent_app_country] => US
[patent_app_date] => 2018-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 3774
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16102431
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/102431 | Dot product based processing elements | Aug 12, 2018 | Issued |
Array
(
[id] => 15714665
[patent_doc_number] => 20200104099
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-02
[patent_title] => CIRCUITS AND DEVICES ADDING BINARY OPERANDS BASED ON VARIABLE QUANTITY
[patent_app_type] => utility
[patent_app_number] => 16/100135
[patent_app_country] => US
[patent_app_date] => 2018-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5480
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16100135
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/100135 | Circuits and devices adding binary operands based on variable quantity | Aug 8, 2018 | Issued |
Array
(
[id] => 13738417
[patent_doc_number] => 20180373678
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-27
[patent_title] => OUTER PRODUCT MULTIPLER SYSTEM AND METHOD
[patent_app_type] => utility
[patent_app_number] => 16/057667
[patent_app_country] => US
[patent_app_date] => 2018-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14736
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057667
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/057667 | Outer product multipler system and method | Aug 6, 2018 | Issued |
Array
(
[id] => 16651924
[patent_doc_number] => 10929101
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-23
[patent_title] => Processor with efficient arithmetic units
[patent_app_type] => utility
[patent_app_number] => 16/056115
[patent_app_country] => US
[patent_app_date] => 2018-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3615
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 256
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16056115
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/056115 | Processor with efficient arithmetic units | Aug 5, 2018 | Issued |
Array
(
[id] => 16032177
[patent_doc_number] => 10678507
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-09
[patent_title] => Programmable multiply-add array hardware
[patent_app_type] => utility
[patent_app_number] => 16/054783
[patent_app_country] => US
[patent_app_date] => 2018-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 3946
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16054783
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/054783 | Programmable multiply-add array hardware | Aug 2, 2018 | Issued |
Array
(
[id] => 13738409
[patent_doc_number] => 20180373674
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-27
[patent_title] => CONVOLUTION ACCELERATORS
[patent_app_type] => utility
[patent_app_number] => 16/052507
[patent_app_country] => US
[patent_app_date] => 2018-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5255
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16052507
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/052507 | CONVOLUTION ACCELERATORS | Jul 31, 2018 | Abandoned |
Array
(
[id] => 13580149
[patent_doc_number] => 20180341623
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-29
[patent_title] => MATRIX CIRCUITS
[patent_app_type] => utility
[patent_app_number] => 16/052516
[patent_app_country] => US
[patent_app_date] => 2018-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6297
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16052516
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/052516 | MATRIX CIRCUITS | Jul 31, 2018 | Abandoned |
Array
(
[id] => 16667450
[patent_doc_number] => 10936697
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-02
[patent_title] => Optimized and scalable sparse triangular linear systems on networks of accelerators
[patent_app_type] => utility
[patent_app_number] => 16/044145
[patent_app_country] => US
[patent_app_date] => 2018-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 9701
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16044145
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/044145 | Optimized and scalable sparse triangular linear systems on networks of accelerators | Jul 23, 2018 | Issued |
Array
(
[id] => 16279133
[patent_doc_number] => 10762164
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-01
[patent_title] => Vector and matrix computing device
[patent_app_type] => utility
[patent_app_number] => 16/039803
[patent_app_country] => US
[patent_app_date] => 2018-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 10044
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16039803
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/039803 | Vector and matrix computing device | Jul 18, 2018 | Issued |
Array
(
[id] => 13845183
[patent_doc_number] => 20190026076
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-24
[patent_title] => NEURAL NETWORK COMPUTING
[patent_app_type] => utility
[patent_app_number] => 16/039221
[patent_app_country] => US
[patent_app_date] => 2018-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6629
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16039221
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/039221 | Neural network computing | Jul 17, 2018 | Issued |
Array
(
[id] => 15058841
[patent_doc_number] => 10459724
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-10-29
[patent_title] => Memory device, and data processing method based on multi-layer RRAM crossbar array
[patent_app_type] => utility
[patent_app_number] => 16/037767
[patent_app_country] => US
[patent_app_date] => 2018-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 9477
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16037767
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/037767 | Memory device, and data processing method based on multi-layer RRAM crossbar array | Jul 16, 2018 | Issued |