Tan V Mai

Array ( [id] => 14669771 [patent_doc_number] => 10372787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Hardware accelerator pre-configured with coefficients for matrix-transform operations [patent_app_type] => utility [patent_app_number] => 15/839229 [patent_app_country] => US [patent_app_date] => 2017-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8231 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15839229 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15231511 [patent_doc_number] => 10503477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Galois field pipelined multiplier with polynomial and beta input passing scheme [patent_app_type] => utility [patent_app_number] => 15/836491 [patent_app_country] => US [patent_app_date] => 2017-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2030 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15836491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14489947 [patent_doc_number] => 10331762 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-25 [patent_title] => Stream processing for LU decomposition [patent_app_type] => utility [patent_app_number] => 15/834301 [patent_app_country] => US [patent_app_date] => 2017-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6021 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15834301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13347109 [patent_doc_number] => 20180225094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => RANDOM NUMBER GENERATING DEVICE AND RANDOM NUMBER GENERATING METHOD [patent_app_type] => utility [patent_app_number] => 15/835115 [patent_app_country] => US [patent_app_date] => 2017-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15835115 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14379065 [patent_doc_number] => 20190163445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => PARALLEL DECIMAL MULTIPLICATION HARDWARE WITH A 3X GENERATOR [patent_app_type] => utility [patent_app_number] => 15/827761 [patent_app_country] => US [patent_app_date] => 2017-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5175 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15827761 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13319255 [patent_doc_number] => 20180211165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => NEUROMORPHIC ARITHMETIC DEVICE [patent_app_type] => utility [patent_app_number] => 15/828153 [patent_app_country] => US [patent_app_date] => 2017-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7061 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15828153 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13540783 [patent_doc_number] => 20180321938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => GENERALIZED ACCELERATION OF MATRIX MULTIPLY ACCUMULATE OPERATIONS [patent_app_type] => utility [patent_app_number] => 15/826435 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21141 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826435 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14736269 [patent_doc_number] => 10387534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Fast matrix multiplication and linear algebra by alternative basis [patent_app_type] => utility [patent_app_number] => 15/823776 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 18350 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15823776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14457457 [patent_doc_number] => 10324689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Scalable memory-optimized hardware for matrix-solve [patent_app_type] => utility [patent_app_number] => 15/819545 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 22973 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15819545 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12757219 [patent_doc_number] => 20180144240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => SEMICONDUCTOR CELL CONFIGURED TO PERFORM LOGIC OPERATIONS [patent_app_type] => utility [patent_app_number] => 15/820239 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8532 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15820239 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13830329 [patent_doc_number] => 20190018649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => NORMALIZATION OF A PRODUCT ON A DATAPATH [patent_app_type] => utility [patent_app_number] => 15/815120 [patent_app_country] => US [patent_app_date] => 2017-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15815120 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13569531 [patent_doc_number] => 20180336313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => ALGEBRAIC PHASING OF POLYPLOIDS [patent_app_type] => utility [patent_app_number] => 15/810242 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810242 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13040951 [patent_doc_number] => 10042610 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => Trailing or leading zero counter having parallel and combinational logic [patent_app_type] => utility [patent_app_number] => 15/810081 [patent_app_country] => US [patent_app_date] => 2017-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8186 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14489239 [patent_doc_number] => 10331407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Tiny detection in a floating-point unit [patent_app_type] => utility [patent_app_number] => 15/810033 [patent_app_country] => US [patent_app_date] => 2017-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5908 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810033 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14298951 [patent_doc_number] => 10289602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Calculation apparatus, displaying method in calculation apparatus, and recording medium [patent_app_type] => utility [patent_app_number] => 15/804617 [patent_app_country] => US [patent_app_date] => 2017-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6329 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15804617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15106215 [patent_doc_number] => 10474432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Repeatable distributed pseudorandom number generation [patent_app_type] => utility [patent_app_number] => 15/801502 [patent_app_country] => US [patent_app_date] => 2017-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 12701 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15801502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14235487 [patent_doc_number] => 20190129916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => COMPUTING USING UNKNOWN VALUES [patent_app_type] => utility [patent_app_number] => 15/802342 [patent_app_country] => US [patent_app_date] => 2017-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13525 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15802342 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13110327 [patent_doc_number] => 10073817 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-09-11 [patent_title] => Optimized matrix multiplication using vector multiplication of interleaved matrix values [patent_app_type] => utility [patent_app_number] => 15/792077 [patent_app_country] => US [patent_app_date] => 2017-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7577 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15792077 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14750569 [patent_doc_number] => 20190258458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => RANDOM NUMBER GENERATOR [patent_app_type] => utility [patent_app_number] => 16/348273 [patent_app_country] => US [patent_app_date] => 2017-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6787 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16348273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13376095 [patent_doc_number] => 20180239589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => ZERO DETECTION OF A SUM OF INPUTS WITHOUT PERFORMING AN ADDITION [patent_app_type] => utility [patent_app_number] => 15/788901 [patent_app_country] => US [patent_app_date] => 2017-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15788901 [rel_patent_id] =>[rel_patent_doc_number] =>)