Tan V Mai

Array ( [id] => 8588255 [patent_doc_number] => 20130007076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'COMPUTATIONALLY EFFICIENT COMPRESSION OF FLOATING-POINT DATA' [patent_app_type] => utility [patent_app_number] => 13/534330 [patent_app_country] => US [patent_app_date] => 2012-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 14777 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13534330 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10228039 [patent_doc_number] => 20150113032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'METHOD AND SYSTEM FOR QUANTIFYING BINARY WORDS SYMMETRY' [patent_app_type] => utility [patent_app_number] => 14/377944 [patent_app_country] => US [patent_app_date] => 2012-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2327 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14377944 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10879084 [patent_doc_number] => 08903880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-02 [patent_title] => 'Trajectory generation system and trajectory generation method' [patent_app_type] => utility [patent_app_number] => 13/495549 [patent_app_country] => US [patent_app_date] => 2012-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5130 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13495549 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8886188 [patent_doc_number] => 20130159371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'Arithmetic Logic Unit Architecture' [patent_app_type] => utility [patent_app_number] => 13/490129 [patent_app_country] => US [patent_app_date] => 2012-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 19401 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13490129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9829248 [patent_doc_number] => 08938484 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-20 [patent_title] => 'Maintaining dependencies among supernodes during repeated matrix factorizations' [patent_app_type] => utility [patent_app_number] => 13/487048 [patent_app_country] => US [patent_app_date] => 2012-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5644 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13487048 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8945835 [patent_doc_number] => 08499022 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-30 [patent_title] => 'Combining multiple clusterings by soft correspondence' [patent_app_type] => utility [patent_app_number] => 13/476100 [patent_app_country] => US [patent_app_date] => 2012-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13476100 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8491227 [patent_doc_number] => 20120290634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'MODULAR EXPONENTIATION METHOD AND DEVICE RESISTANT AGAINST SIDE-CHANNEL ATTACKS' [patent_app_type] => utility [patent_app_number] => 13/469139 [patent_app_country] => US [patent_app_date] => 2012-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2665 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13469139 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9940444 [patent_doc_number] => 08990274 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-03-24 [patent_title] => 'Generating a presentation associated with a set of instructions' [patent_app_type] => utility [patent_app_number] => 13/468985 [patent_app_country] => US [patent_app_date] => 2012-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9147 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13468985 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9752050 [patent_doc_number] => 08843539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-23 [patent_title] => 'Generation of seed value for pseudo random number generator' [patent_app_type] => utility [patent_app_number] => 13/466974 [patent_app_country] => US [patent_app_date] => 2012-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4868 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13466974 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9136952 [patent_doc_number] => 20130297667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'OSBS subtractor Accelerator' [patent_app_type] => utility [patent_app_number] => 13/506637 [patent_app_country] => US [patent_app_date] => 2012-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10506 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13506637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8485058 [patent_doc_number] => 20120284464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'Zero Overhead Block Floating Point Implementation in CPU\'s' [patent_app_type] => utility [patent_app_number] => 13/461902 [patent_app_country] => US [patent_app_date] => 2012-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12295 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13461902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8360667 [patent_doc_number] => 20120215826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-23 [patent_title] => 'SYSTEM AND METHOD TO IMPLEMENT A MATRIX MULTIPLY UNIT OF A BROADBAND PROCESSOR' [patent_app_type] => utility [patent_app_number] => 13/462648 [patent_app_country] => US [patent_app_date] => 2012-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5214 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13462648 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8360661 [patent_doc_number] => 20120215821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-23 [patent_title] => 'SYSTEMS, DEVICES, AND METHODS FOR SOLVING COMPUTATIONAL PROBLEMS' [patent_app_type] => utility [patent_app_number] => 13/462494 [patent_app_country] => US [patent_app_date] => 2012-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11161 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13462494 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9472140 [patent_doc_number] => 08725787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-13 [patent_title] => 'Processor for performing multiply-add operations on packed data' [patent_app_type] => utility [patent_app_number] => 13/456761 [patent_app_country] => US [patent_app_date] => 2012-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 9611 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13456761 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10834461 [patent_doc_number] => 08862653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-14 [patent_title] => 'System and method for sparse matrix vector multiplication processing' [patent_app_type] => utility [patent_app_number] => 13/456657 [patent_app_country] => US [patent_app_date] => 2012-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6825 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13456657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10872996 [patent_doc_number] => 08898214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Method and apparatus to perform floating point operations' [patent_app_type] => utility [patent_app_number] => 13/453056 [patent_app_country] => US [patent_app_date] => 2012-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7601 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13453056 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9385888 [patent_doc_number] => 20140089371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'MIXED PRECISION FUSED MULTIPLY-ADD OPERATOR' [patent_app_type] => utility [patent_app_number] => 14/113636 [patent_app_country] => US [patent_app_date] => 2012-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4703 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14113636 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8337110 [patent_doc_number] => 20120203813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'GENERATION OF TEST CASES WITH RANGE CONSTRAINTS FOR FLOATING POINT ADD AND SUBTRACT INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 13/448761 [patent_app_country] => US [patent_app_date] => 2012-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 16774 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13448761 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10894813 [patent_doc_number] => 08918444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-23 [patent_title] => 'Method and device for filterling an input signal' [patent_app_type] => utility [patent_app_number] => 13/432882 [patent_app_country] => US [patent_app_date] => 2012-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2891 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13432882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8504281 [patent_doc_number] => 20120303689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'ARITHMETIC CIRCUIT AND A/D CONVERTER' [patent_app_type] => utility [patent_app_number] => 13/426528 [patent_app_country] => US [patent_app_date] => 2012-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4950 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13426528 [rel_patent_id] =>[rel_patent_doc_number] =>)