Search

Tan V Mai

Examiner (ID: 13419, Phone: (571)272-3726 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2787, 2183, 2121, 2182, 2193, 2301, 2306, 2124, 2786, 2302
Total Applications
3863
Issued Applications
3431
Pending Applications
94
Abandoned Applications
349

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8507618 [patent_doc_number] => 20120307025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'METHOD AND ELECTRONIC CIRCUIT FOR READING THE SIGNALS GENERATED BY ONE OR MORE PIXELATED SENSORS' [patent_app_type] => utility [patent_app_number] => 13/504041 [patent_app_country] => US [patent_app_date] => 2010-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8178 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13504041 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/504041
Method and electronic circuit for reading the signals generated by one or more pixelated sensors Oct 25, 2010 Issued
Array ( [id] => 9012250 [patent_doc_number] => 08527568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'Efficient computation of sketches' [patent_app_type] => utility [patent_app_number] => 12/910758 [patent_app_country] => US [patent_app_date] => 2010-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6870 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12910758 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/910758
Efficient computation of sketches Oct 21, 2010 Issued
Array ( [id] => 9326035 [patent_doc_number] => 08661071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-25 [patent_title] => 'Systems and methods for partially conditioned noise predictive equalization' [patent_app_type] => utility [patent_app_number] => 12/901742 [patent_app_country] => US [patent_app_date] => 2010-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9004 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12901742 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/901742
Systems and methods for partially conditioned noise predictive equalization Oct 10, 2010 Issued
Array ( [id] => 10866895 [patent_doc_number] => 08892620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-18 [patent_title] => 'Computer for Amdahl-compliant algorithms like matrix inversion' [patent_app_type] => utility [patent_app_number] => 13/500103 [patent_app_country] => US [patent_app_date] => 2010-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 43 [patent_no_of_words] => 13528 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13500103 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/500103
Computer for Amdahl-compliant algorithms like matrix inversion Oct 6, 2010 Issued
Array ( [id] => 9289087 [patent_doc_number] => 08645439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-04 [patent_title] => 'Bit-width allocation for scientific computations' [patent_app_type] => utility [patent_app_number] => 12/897652 [patent_app_country] => US [patent_app_date] => 2010-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 12536 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12897652 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/897652
Bit-width allocation for scientific computations Oct 3, 2010 Issued
Array ( [id] => 9049069 [patent_doc_number] => 08543627 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-24 [patent_title] => 'Method for sampling probability distributions using a quantum computer' [patent_app_type] => utility [patent_app_number] => 12/924654 [patent_app_country] => US [patent_app_date] => 2010-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4463 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12924654 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/924654
Method for sampling probability distributions using a quantum computer Sep 30, 2010 Issued
Array ( [id] => 8097461 [patent_doc_number] => 20120084336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => 'Systems and Methods for Retry Sync Mark Detection' [patent_app_type] => utility [patent_app_number] => 12/894221 [patent_app_country] => US [patent_app_date] => 2010-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8241 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20120084336.pdf [firstpage_image] =>[orig_patent_app_number] => 12894221 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/894221
Systems and methods for retry sync mark detection Sep 29, 2010 Issued
Array ( [id] => 8059017 [patent_doc_number] => 20120079240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'Reduced-Level Shift Overflow Detection' [patent_app_type] => utility [patent_app_number] => 12/891718 [patent_app_country] => US [patent_app_date] => 2010-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5389 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20120079240.pdf [firstpage_image] =>[orig_patent_app_number] => 12891718 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/891718
Reduced-level shift overflow detection Sep 26, 2010 Issued
Array ( [id] => 9115962 [patent_doc_number] => 08572154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'Reduced-level two\'s complement arithmetic unit' [patent_app_type] => utility [patent_app_number] => 12/891708 [patent_app_country] => US [patent_app_date] => 2010-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3195 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12891708 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/891708
Reduced-level two's complement arithmetic unit Sep 26, 2010 Issued
Array ( [id] => 8878553 [patent_doc_number] => 08473537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Secure multi-party computation of normalized sum-type functions' [patent_app_type] => utility [patent_app_number] => 12/890151 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5455 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12890151 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/890151
Secure multi-party computation of normalized sum-type functions Sep 23, 2010 Issued
Array ( [id] => 8059043 [patent_doc_number] => 20120079250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'FUNCTIONAL UNIT CAPABLE OF EXECUTING APPROXIMATIONS OF FUNCTIONS' [patent_app_type] => utility [patent_app_number] => 12/890533 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4794 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20120079250.pdf [firstpage_image] =>[orig_patent_app_number] => 12890533 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/890533
Functional unit capable of executing approximations of functions Sep 23, 2010 Issued
Array ( [id] => 9049075 [patent_doc_number] => 08543633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-24 [patent_title] => 'Modified Gram-Schmidt core implemented in a single field programmable gate array architecture' [patent_app_type] => utility [patent_app_number] => 12/889988 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 6141 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12889988 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/889988
Modified Gram-Schmidt core implemented in a single field programmable gate array architecture Sep 23, 2010 Issued
Array ( [id] => 6124791 [patent_doc_number] => 20110078225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'Extended-Precision Integer Arithmetic and Logical Instructions' [patent_app_type] => utility [patent_app_number] => 12/889354 [patent_app_country] => US [patent_app_date] => 2010-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11657 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20110078225.pdf [firstpage_image] =>[orig_patent_app_number] => 12889354 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/889354
Extended-precision integer arithmetic and logical instructions Sep 22, 2010 Issued
Array ( [id] => 8050571 [patent_doc_number] => 20120075012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'Systems and Methods for Filter Initialization and Tuning' [patent_app_type] => utility [patent_app_number] => 12/889288 [patent_app_country] => US [patent_app_date] => 2010-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8051 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20120075012.pdf [firstpage_image] =>[orig_patent_app_number] => 12889288 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/889288
Systems and methods for filter initialization and tuning Sep 22, 2010 Issued
Array ( [id] => 9143228 [patent_doc_number] => 08583710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-12 [patent_title] => 'Identification circuit and method for generating an identification bit using physical unclonable functions' [patent_app_type] => utility [patent_app_number] => 12/885329 [patent_app_country] => US [patent_app_date] => 2010-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4073 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12885329 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/885329
Identification circuit and method for generating an identification bit using physical unclonable functions Sep 16, 2010 Issued
Array ( [id] => 8775240 [patent_doc_number] => 08429214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-23 [patent_title] => 'Programmable logic systems and methods employing configurable floating point units' [patent_app_type] => utility [patent_app_number] => 12/885103 [patent_app_country] => US [patent_app_date] => 2010-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 6391 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12885103 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/885103
Programmable logic systems and methods employing configurable floating point units Sep 16, 2010 Issued
Array ( [id] => 9077233 [patent_doc_number] => 08554824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Efficient technique for optimal re-use of hardware in the implementation of instructions used in viterbi, turbo and LPDC decoders' [patent_app_type] => utility [patent_app_number] => 12/874699 [patent_app_country] => US [patent_app_date] => 2010-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3889 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12874699 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/874699
Efficient technique for optimal re-use of hardware in the implementation of instructions used in viterbi, turbo and LPDC decoders Sep 1, 2010 Issued
Array ( [id] => 9077232 [patent_doc_number] => 08554823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Technique for optimization and re-use of hardware in the implementation of instructions used in viterbi and turbo decoding, using carry and save arithmetic' [patent_app_type] => utility [patent_app_number] => 12/874653 [patent_app_country] => US [patent_app_date] => 2010-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3881 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12874653 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/874653
Technique for optimization and re-use of hardware in the implementation of instructions used in viterbi and turbo decoding, using carry and save arithmetic Sep 1, 2010 Issued
Array ( [id] => 6190960 [patent_doc_number] => 20110173244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'STATE FILTER' [patent_app_type] => utility [patent_app_number] => 12/869342 [patent_app_country] => US [patent_app_date] => 2010-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12476 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20110173244.pdf [firstpage_image] =>[orig_patent_app_number] => 12869342 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/869342
State filter Aug 25, 2010 Issued
Array ( [id] => 7785637 [patent_doc_number] => 20120047193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-23 [patent_title] => 'LOCUS SMOOTHING METHOD' [patent_app_type] => utility [patent_app_number] => 12/859535 [patent_app_country] => US [patent_app_date] => 2010-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2857 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20120047193.pdf [firstpage_image] =>[orig_patent_app_number] => 12859535 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/859535
Locus smoothing method Aug 18, 2010 Issued
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