Search

Tan V Mai

Examiner (ID: 15743, Phone: (571)272-3726 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2306, 2193, 2787, 2786, 2121, 2124, 2302, 2301, 2182, 2183
Total Applications
3863
Issued Applications
3431
Pending Applications
94
Abandoned Applications
349

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4712686 [patent_doc_number] => 20080301212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'REAL TIME UNIVERSAL DATE AND TIME CONVERSION' [patent_app_type] => utility [patent_app_number] => 12/129994 [patent_app_country] => US [patent_app_date] => 2008-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4602 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0301/20080301212.pdf [firstpage_image] =>[orig_patent_app_number] => 12129994 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/129994
Real time universal date and time conversion May 29, 2008 Issued
Array ( [id] => 8235271 [patent_doc_number] => 08200728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-12 [patent_title] => 'Sine/cosine generator' [patent_app_type] => utility [patent_app_number] => 12/129654 [patent_app_country] => US [patent_app_date] => 2008-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10134 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/200/08200728.pdf [firstpage_image] =>[orig_patent_app_number] => 12129654 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/129654
Sine/cosine generator May 28, 2008 Issued
Array ( [id] => 4861658 [patent_doc_number] => 20080270501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'Seed generating circuit, random number generating circuit, semiconductor integrated circuit, IC card, and information terminal equipment' [patent_app_type] => utility [patent_app_number] => 12/153410 [patent_app_country] => US [patent_app_date] => 2008-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6903 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270501.pdf [firstpage_image] =>[orig_patent_app_number] => 12153410 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/153410
Seed generating circuit, random number generating circuit, semiconductor integrated circuit, IC card, and information terminal equipment May 18, 2008 Issued
Array ( [id] => 4665247 [patent_doc_number] => 20080256154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'Method and Apparatus for Synthesizing a User Defined Pre-Emphasized Arbitrary Waveform for High Speed Serial Data Technologies' [patent_app_type] => utility [patent_app_number] => 12/111173 [patent_app_country] => US [patent_app_date] => 2008-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2988 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20080256154.pdf [firstpage_image] =>[orig_patent_app_number] => 12111173 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/111173
Method and Apparatus for Synthesizing a User Defined Pre-Emphasized Arbitrary Waveform for High Speed Serial Data Technologies Apr 27, 2008 Abandoned
Array ( [id] => 8740976 [patent_doc_number] => 08412762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-02 [patent_title] => 'Error-correcting method used in data transmission and decoding' [patent_app_type] => utility [patent_app_number] => 12/110912 [patent_app_country] => US [patent_app_date] => 2008-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2036 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12110912 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/110912
Error-correcting method used in data transmission and decoding Apr 27, 2008 Issued
Array ( [id] => 8997896 [patent_doc_number] => 08521801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Configurable hybrid adder circuitry' [patent_app_type] => utility [patent_app_number] => 12/111156 [patent_app_country] => US [patent_app_date] => 2008-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 17 [patent_no_of_words] => 6600 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12111156 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/111156
Configurable hybrid adder circuitry Apr 27, 2008 Issued
Array ( [id] => 4841410 [patent_doc_number] => 20080281896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'INDUSTRIAL CONTROLLER' [patent_app_type] => utility [patent_app_number] => 12/108774 [patent_app_country] => US [patent_app_date] => 2008-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6772 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20080281896.pdf [firstpage_image] =>[orig_patent_app_number] => 12108774 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/108774
Industrial controller Apr 23, 2008 Issued
Array ( [id] => 288145 [patent_doc_number] => 07552164 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-23 [patent_title] => 'Accelerated prime sieving using architecture-optimized partial prime product table' [patent_app_type] => utility [patent_app_number] => 12/108513 [patent_app_country] => US [patent_app_date] => 2008-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3061 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 502 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/552/07552164.pdf [firstpage_image] =>[orig_patent_app_number] => 12108513 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/108513
Accelerated prime sieving using architecture-optimized partial prime product table Apr 23, 2008 Issued
Array ( [id] => 8010485 [patent_doc_number] => 08086657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-27 [patent_title] => 'Adder structure with midcycle latch for power reduction' [patent_app_type] => utility [patent_app_number] => 12/099973 [patent_app_country] => US [patent_app_date] => 2008-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 4367 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/086/08086657.pdf [firstpage_image] =>[orig_patent_app_number] => 12099973 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/099973
Adder structure with midcycle latch for power reduction Apr 8, 2008 Issued
Array ( [id] => 8804743 [patent_doc_number] => 08443025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Method and apparatus for selectively reducing noise in a digital signal' [patent_app_type] => utility [patent_app_number] => 12/450746 [patent_app_country] => US [patent_app_date] => 2008-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4760 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12450746 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/450746
Method and apparatus for selectively reducing noise in a digital signal Apr 7, 2008 Issued
Array ( [id] => 265427 [patent_doc_number] => 07571201 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-08-04 [patent_title] => 'Method for distributed joint pseudo random decision making' [patent_app_type] => utility [patent_app_number] => 12/061808 [patent_app_country] => US [patent_app_date] => 2008-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1622 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/571/07571201.pdf [firstpage_image] =>[orig_patent_app_number] => 12061808 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/061808
Method for distributed joint pseudo random decision making Apr 2, 2008 Issued
Array ( [id] => 8692951 [patent_doc_number] => 08392487 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-03-05 [patent_title] => 'Programmable matrix processor' [patent_app_type] => utility [patent_app_number] => 12/058783 [patent_app_country] => US [patent_app_date] => 2008-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5025 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12058783 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/058783
Programmable matrix processor Mar 30, 2008 Issued
Array ( [id] => 597606 [patent_doc_number] => 07451171 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-11-11 [patent_title] => 'Systems, methods and computer program products for hardware assists for microcoded floating point divide and square root' [patent_app_type] => utility [patent_app_number] => 12/059055 [patent_app_country] => US [patent_app_date] => 2008-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4185 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/451/07451171.pdf [firstpage_image] =>[orig_patent_app_number] => 12059055 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/059055
Systems, methods and computer program products for hardware assists for microcoded floating point divide and square root Mar 30, 2008 Issued
Array ( [id] => 8342852 [patent_doc_number] => 08244789 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-14 [patent_title] => 'Normalization of floating point operations in a programmable integrated circuit device' [patent_app_type] => utility [patent_app_number] => 12/048379 [patent_app_country] => US [patent_app_date] => 2008-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4551 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12048379 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/048379
Normalization of floating point operations in a programmable integrated circuit device Mar 13, 2008 Issued
Array ( [id] => 7537479 [patent_doc_number] => 08051121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'Dual multiply-accumulator operation optimized for even and odd multisample calculations' [patent_app_type] => utility [patent_app_number] => 12/042100 [patent_app_country] => US [patent_app_date] => 2008-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5045 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/051/08051121.pdf [firstpage_image] =>[orig_patent_app_number] => 12042100 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/042100
Dual multiply-accumulator operation optimized for even and odd multisample calculations Mar 3, 2008 Issued
Array ( [id] => 4754820 [patent_doc_number] => 20080162896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'APPARATUS AND METHOD FOR GENERATING PACKED SUM OF ABSOLUTE DIFFERENCES' [patent_app_type] => utility [patent_app_number] => 12/037596 [patent_app_country] => US [patent_app_date] => 2008-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4558 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20080162896.pdf [firstpage_image] =>[orig_patent_app_number] => 12037596 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/037596
Apparatus and method for generating packed sum of absolute differences Feb 25, 2008 Issued
Array ( [id] => 8460665 [patent_doc_number] => 08296348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Encoding and decoding data arrays' [patent_app_type] => utility [patent_app_number] => 12/037061 [patent_app_country] => US [patent_app_date] => 2008-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3748 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12037061 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/037061
Encoding and decoding data arrays Feb 24, 2008 Issued
Array ( [id] => 4874662 [patent_doc_number] => 20080201396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'Signal processing apparatus and the correcting method' [patent_app_type] => utility [patent_app_number] => 12/010985 [patent_app_country] => US [patent_app_date] => 2008-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5516 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20080201396.pdf [firstpage_image] =>[orig_patent_app_number] => 12010985 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/010985
Signal processing apparatus and the correcting method Jan 30, 2008 Issued
Array ( [id] => 4874662 [patent_doc_number] => 20080201396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'Signal processing apparatus and the correcting method' [patent_app_type] => utility [patent_app_number] => 12/010985 [patent_app_country] => US [patent_app_date] => 2008-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5516 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20080201396.pdf [firstpage_image] =>[orig_patent_app_number] => 12010985 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/010985
Signal processing apparatus and the correcting method Jan 30, 2008 Issued
Array ( [id] => 4874662 [patent_doc_number] => 20080201396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'Signal processing apparatus and the correcting method' [patent_app_type] => utility [patent_app_number] => 12/010985 [patent_app_country] => US [patent_app_date] => 2008-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5516 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20080201396.pdf [firstpage_image] =>[orig_patent_app_number] => 12010985 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/010985
Signal processing apparatus and the correcting method Jan 30, 2008 Issued
Menu