Search

Tan V Mai

Examiner (ID: 15743, Phone: (571)272-3726 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2306, 2193, 2787, 2786, 2121, 2124, 2302, 2301, 2182, 2183
Total Applications
3863
Issued Applications
3431
Pending Applications
94
Abandoned Applications
349

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7705754 [patent_doc_number] => 08090757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-03 [patent_title] => 'Circuit and method for performing multiple modulo mathematic operations' [patent_app_type] => utility [patent_app_number] => 11/987092 [patent_app_country] => US [patent_app_date] => 2007-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 9714 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/090/08090757.pdf [firstpage_image] =>[orig_patent_app_number] => 11987092 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/987092
Circuit and method for performing multiple modulo mathematic operations Nov 26, 2007 Issued
Array ( [id] => 5565683 [patent_doc_number] => 20090138536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-28 [patent_title] => 'PRECISION-SENSING LINEAR INTERPOLATION ALGORITHM' [patent_app_type] => utility [patent_app_number] => 11/945912 [patent_app_country] => US [patent_app_date] => 2007-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1761 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20090138536.pdf [firstpage_image] =>[orig_patent_app_number] => 11945912 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/945912
PRECISION-SENSING LINEAR INTERPOLATION ALGORITHM Nov 26, 2007 Abandoned
Array ( [id] => 8219679 [patent_doc_number] => 08195734 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-06-05 [patent_title] => 'Combining multiple clusterings by soft correspondence' [patent_app_type] => utility [patent_app_number] => 11/945956 [patent_app_country] => US [patent_app_date] => 2007-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9114 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/195/08195734.pdf [firstpage_image] =>[orig_patent_app_number] => 11945956 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/945956
Combining multiple clusterings by soft correspondence Nov 26, 2007 Issued
Array ( [id] => 8000871 [patent_doc_number] => 08082283 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-20 [patent_title] => 'Arrangement of 3-input LUT\'S to implement 4:2 compressors for multiple operand arithmetic' [patent_app_type] => utility [patent_app_number] => 11/945194 [patent_app_country] => US [patent_app_date] => 2007-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2115 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/082/08082283.pdf [firstpage_image] =>[orig_patent_app_number] => 11945194 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/945194
Arrangement of 3-input LUT'S to implement 4:2 compressors for multiple operand arithmetic Nov 25, 2007 Issued
Array ( [id] => 8272899 [patent_doc_number] => 08214418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'Method for combining binary numbers in environments having limited bit widths and apparatus therefor' [patent_app_type] => utility [patent_app_number] => 11/984603 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6326 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11984603 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/984603
Method for combining binary numbers in environments having limited bit widths and apparatus therefor Nov 19, 2007 Issued
Array ( [id] => 5280662 [patent_doc_number] => 20090132794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'Method and apparatus for performing complex calculations in a multiprocessor array' [patent_app_type] => utility [patent_app_number] => 11/985870 [patent_app_country] => US [patent_app_date] => 2007-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2070 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20090132794.pdf [firstpage_image] =>[orig_patent_app_number] => 11985870 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/985870
Method and apparatus for performing complex calculations in a multiprocessor array Nov 15, 2007 Issued
Array ( [id] => 8872803 [patent_doc_number] => 08468189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-18 [patent_title] => 'Iterated variational regularization combined with componentwise regularization' [patent_app_type] => utility [patent_app_number] => 12/513943 [patent_app_country] => US [patent_app_date] => 2007-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 10803 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12513943 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/513943
Iterated variational regularization combined with componentwise regularization Nov 7, 2007 Issued
Array ( [id] => 4808861 [patent_doc_number] => 20080172439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-17 [patent_title] => 'METHOD AND DEVICE FOR DIGITIZING AN ANALOGICAL SIGNAL' [patent_app_type] => utility [patent_app_number] => 11/936107 [patent_app_country] => US [patent_app_date] => 2007-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2003 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20080172439.pdf [firstpage_image] =>[orig_patent_app_number] => 11936107 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/936107
Method and device for digitizing an analogical signal Nov 6, 2007 Issued
Array ( [id] => 7982273 [patent_doc_number] => 08073894 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-06 [patent_title] => 'Compact switched-capacitor FIR filter implementation' [patent_app_type] => utility [patent_app_number] => 11/935815 [patent_app_country] => US [patent_app_date] => 2007-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8171 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/073/08073894.pdf [firstpage_image] =>[orig_patent_app_number] => 11935815 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/935815
Compact switched-capacitor FIR filter implementation Nov 5, 2007 Issued
Array ( [id] => 5328406 [patent_doc_number] => 20090108883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'Digital sine wave generator' [patent_app_type] => utility [patent_app_number] => 11/982264 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2788 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20090108883.pdf [firstpage_image] =>[orig_patent_app_number] => 11982264 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/982264
Digital sine wave generator Oct 30, 2007 Issued
Array ( [id] => 7547715 [patent_doc_number] => 08055696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Modular multiplication method, modular multiplier and cryptosystem having the same' [patent_app_type] => utility [patent_app_number] => 11/980360 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7657 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/055/08055696.pdf [firstpage_image] =>[orig_patent_app_number] => 11980360 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/980360
Modular multiplication method, modular multiplier and cryptosystem having the same Oct 30, 2007 Issued
Array ( [id] => 4940452 [patent_doc_number] => 20080077771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'Long Instruction Word Controlling Plural Independent Processor Operations' [patent_app_type] => utility [patent_app_number] => 11/930652 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 99033 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20080077771.pdf [firstpage_image] =>[orig_patent_app_number] => 11930652 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/930652
Long Instruction Word Controlling Plural Independent Processor Operations Oct 30, 2007 Abandoned
Array ( [id] => 4706188 [patent_doc_number] => 20080065712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'Automated data alignment based upon indirect device relationships' [patent_app_type] => utility [patent_app_number] => 11/981428 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 21598 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20080065712.pdf [firstpage_image] =>[orig_patent_app_number] => 11981428 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/981428
Automated data alignment based upon indirect device relationships Oct 30, 2007 Issued
Array ( [id] => 8460663 [patent_doc_number] => 08296347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Use of line characterization to configure physical layered devices' [patent_app_type] => utility [patent_app_number] => 11/981565 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1949 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11981565 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/981565
Use of line characterization to configure physical layered devices Oct 29, 2007 Issued
Array ( [id] => 4507234 [patent_doc_number] => 07958179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Arithmetic method and device of reconfigurable processor' [patent_app_type] => utility [patent_app_number] => 11/978878 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2622 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/958/07958179.pdf [firstpage_image] =>[orig_patent_app_number] => 11978878 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/978878
Arithmetic method and device of reconfigurable processor Oct 29, 2007 Issued
Array ( [id] => 8354785 [patent_doc_number] => 08250128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-21 [patent_title] => 'Apparatus and methods for autonomous testing of random number generators' [patent_app_type] => utility [patent_app_number] => 11/978464 [patent_app_country] => US [patent_app_date] => 2007-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5593 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11978464 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/978464
Apparatus and methods for autonomous testing of random number generators Oct 28, 2007 Issued
Array ( [id] => 7553013 [patent_doc_number] => 08065355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Interpolation FIR filter having multiple data rates in mobile communication system and method of filtering data using the same' [patent_app_type] => utility [patent_app_number] => 11/925712 [patent_app_country] => US [patent_app_date] => 2007-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5668 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/065/08065355.pdf [firstpage_image] =>[orig_patent_app_number] => 11925712 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/925712
Interpolation FIR filter having multiple data rates in mobile communication system and method of filtering data using the same Oct 25, 2007 Issued
Array ( [id] => 8667305 [patent_doc_number] => 08380778 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-19 [patent_title] => 'System, method, and computer program product for assigning elements of a matrix to processing threads with increased contiguousness' [patent_app_type] => utility [patent_app_number] => 11/924379 [patent_app_country] => US [patent_app_date] => 2007-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4515 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11924379 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/924379
System, method, and computer program product for assigning elements of a matrix to processing threads with increased contiguousness Oct 24, 2007 Issued
Array ( [id] => 4754821 [patent_doc_number] => 20080162897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Binary Logic Unit and Method to Operate a Binary Logic Unit' [patent_app_type] => utility [patent_app_number] => 11/872846 [patent_app_country] => US [patent_app_date] => 2007-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4876 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20080162897.pdf [firstpage_image] =>[orig_patent_app_number] => 11872846 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/872846
Binary logic unit and method to operate a binary logic unit Oct 15, 2007 Issued
Array ( [id] => 4832325 [patent_doc_number] => 20080130871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'Permute Unit and Method to Operate a Permute Unit' [patent_app_type] => utility [patent_app_number] => 11/872811 [patent_app_country] => US [patent_app_date] => 2007-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4446 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20080130871.pdf [firstpage_image] =>[orig_patent_app_number] => 11872811 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/872811
Permute unit and method to operate a permute unit Oct 15, 2007 Issued
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