Tan V Mai

Array ( [id] => 4861654 [patent_doc_number] => 20080270500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'COMPOSITION OF DECIMAL FLOATING POINT DATA, AND METHODS THEREFOR' [patent_app_type] => utility [patent_app_number] => 11/840323 [patent_app_country] => US [patent_app_date] => 2007-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17150 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270500.pdf [firstpage_image] =>[orig_patent_app_number] => 11840323 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4861649 [patent_doc_number] => 20080270499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'DECOMPOSITION OF DECIMAL FLOATING POINT DATA' [patent_app_type] => utility [patent_app_number] => 11/840345 [patent_app_country] => US [patent_app_date] => 2007-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17256 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270499.pdf [firstpage_image] =>[orig_patent_app_number] => 11840345 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8000869 [patent_doc_number] => 08082282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-20 [patent_title] => 'Decomposition of decimal floating point data, and methods therefor' [patent_app_type] => utility [patent_app_number] => 11/840359 [patent_app_country] => US [patent_app_date] => 2007-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 30 [patent_no_of_words] => 17231 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/082/08082282.pdf [firstpage_image] =>[orig_patent_app_number] => 11840359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8997895 [patent_doc_number] => 08521800 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-27 [patent_title] => 'Interconnected arithmetic logic units' [patent_app_type] => utility [patent_app_number] => 11/893498 [patent_app_country] => US [patent_app_date] => 2007-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5480 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11893498 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4442831 [patent_doc_number] => 07899858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Filter circuit' [patent_app_type] => utility [patent_app_number] => 11/834740 [patent_app_country] => US [patent_app_date] => 2007-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4386 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/899/07899858.pdf [firstpage_image] =>[orig_patent_app_number] => 11834740 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5362711 [patent_doc_number] => 20090037505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'INTERPOLATING CUBIC SPLINE FILTER AND METHOD' [patent_app_type] => utility [patent_app_number] => 11/833039 [patent_app_country] => US [patent_app_date] => 2007-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3786 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20090037505.pdf [firstpage_image] =>[orig_patent_app_number] => 11833039 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5362710 [patent_doc_number] => 20090037504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'Exponent Processing Systems and Methods' [patent_app_type] => utility [patent_app_number] => 11/832689 [patent_app_country] => US [patent_app_date] => 2007-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6530 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20090037504.pdf [firstpage_image] =>[orig_patent_app_number] => 11832689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4861648 [patent_doc_number] => 20080270498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'CONVERT SIGNIFICAND OF DECIMAL FLOATING POINT DATA TO PACKED DECIMAL FORMAT' [patent_app_type] => utility [patent_app_number] => 11/781574 [patent_app_country] => US [patent_app_date] => 2007-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17249 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270498.pdf [firstpage_image] =>[orig_patent_app_number] => 11781574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4861671 [patent_doc_number] => 20080270506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'CONVERT SIGNIFICAND OF DECIMAL FLOATING POINT DATA FROM PACKED DECIMAL FORMAT' [patent_app_type] => utility [patent_app_number] => 11/781650 [patent_app_country] => US [patent_app_date] => 2007-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17248 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270506.pdf [firstpage_image] =>[orig_patent_app_number] => 11781650 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9629647 [patent_doc_number] => 08799341 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-05 [patent_title] => 'Multi-dimensional hybrid and transpose form finite impulse response filters' [patent_app_type] => utility [patent_app_number] => 11/781313 [patent_app_country] => US [patent_app_date] => 2007-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2739 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11781313 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5291952 [patent_doc_number] => 20090024682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-22 [patent_title] => 'Determining an approximate number of instances of an item for an organization' [patent_app_type] => utility [patent_app_number] => 11/880135 [patent_app_country] => US [patent_app_date] => 2007-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4907 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20090024682.pdf [firstpage_image] =>[orig_patent_app_number] => 11880135 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7767840 [patent_doc_number] => 08117247 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-02-14 [patent_title] => 'Configurable arithmetic block and method of implementing arithmetic functions in a device having programmable logic' [patent_app_type] => utility [patent_app_number] => 11/880140 [patent_app_country] => US [patent_app_date] => 2007-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 28 [patent_no_of_words] => 15437 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/117/08117247.pdf [firstpage_image] =>[orig_patent_app_number] => 11880140 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4911175 [patent_doc_number] => 20080021942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'Arrangements for evaluating boolean functions' [patent_app_type] => utility [patent_app_number] => 11/880042 [patent_app_country] => US [patent_app_date] => 2007-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5247 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20080021942.pdf [firstpage_image] =>[orig_patent_app_number] => 11880042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4631680 [patent_doc_number] => 08010590 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-08-30 [patent_title] => 'Configurable arithmetic block and a method of implementing a configurable arithmetic block in a device having programmable logic' [patent_app_type] => utility [patent_app_number] => 11/880141 [patent_app_country] => US [patent_app_date] => 2007-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 28 [patent_no_of_words] => 15437 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/010/08010590.pdf [firstpage_image] =>[orig_patent_app_number] => 11880141 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4487301 [patent_doc_number] => 07908307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-15 [patent_title] => 'Filter bank and method for improving efficiency thereof' [patent_app_type] => utility [patent_app_number] => 11/778230 [patent_app_country] => US [patent_app_date] => 2007-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4458 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/908/07908307.pdf [firstpage_image] =>[orig_patent_app_number] => 11778230 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4526595 [patent_doc_number] => 07933944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-26 [patent_title] => 'Combined fast multipole-QR compression technique for solving electrically small to large structures for broadband applications' [patent_app_type] => utility [patent_app_number] => 11/778369 [patent_app_country] => US [patent_app_date] => 2007-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 6737 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/933/07933944.pdf [firstpage_image] =>[orig_patent_app_number] => 11778369 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5311819 [patent_doc_number] => 20090019100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'POPULATION COUNT APPROXIMATION CIRCUIT AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/777664 [patent_app_country] => US [patent_app_date] => 2007-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5583 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20090019100.pdf [firstpage_image] =>[orig_patent_app_number] => 11777664 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4442819 [patent_doc_number] => 07899852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Systems, methods, and apparatus for quasi-adiabatic quantum computation' [patent_app_type] => utility [patent_app_number] => 11/777910 [patent_app_country] => US [patent_app_date] => 2007-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9387 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/899/07899852.pdf [firstpage_image] =>[orig_patent_app_number] => 11777910 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5351156 [patent_doc_number] => 20090006517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'UNIFIED INTEGER/GALOIS FIELD (2m) MULTIPLIER ARCHITECTURE FOR ELLIPTIC-CURVE CRYTPOGRAPHY' [patent_app_type] => utility [patent_app_number] => 11/772166 [patent_app_country] => US [patent_app_date] => 2007-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6407 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20090006517.pdf [firstpage_image] =>[orig_patent_app_number] => 11772166 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4656435 [patent_doc_number] => 20080025296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'Conditional Selection Adder and Method of Conditional Selection Adding' [patent_app_type] => utility [patent_app_number] => 11/769016 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4837 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20080025296.pdf [firstpage_image] =>[orig_patent_app_number] => 11769016 [rel_patent_id] =>[rel_patent_doc_number] =>)