Search

Tan V. Mai

Examiner (ID: 15743)

Most Active Art Unit
2193
Art Unit(s)
2306, 2193, 2787, 2786, 2121, 2124, 2302, 2301, 2182, 2183
Total Applications
3863
Issued Applications
3431
Pending Applications
94
Abandoned Applications
349

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5739800 [patent_doc_number] => 20060010191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'Circuit and method for performing multiple modulo mathematic operations' [patent_app_type] => utility [patent_app_number] => 11/228552 [patent_app_country] => US [patent_app_date] => 2005-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9681 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20060010191.pdf [firstpage_image] =>[orig_patent_app_number] => 11228552 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/228552
Circuit and method for performing multiple modulo mathematic operations Sep 15, 2005 Issued
Array ( [id] => 135961 [patent_doc_number] => 07702710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-20 [patent_title] => 'Digital signal processor optimized for interpolation and decimation' [patent_app_type] => utility [patent_app_number] => 11/224495 [patent_app_country] => US [patent_app_date] => 2005-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 6135 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/702/07702710.pdf [firstpage_image] =>[orig_patent_app_number] => 11224495 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/224495
Digital signal processor optimized for interpolation and decimation Sep 11, 2005 Issued
Array ( [id] => 5127543 [patent_doc_number] => 20070239814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'Statistical control of adaptive ocular filter stability' [patent_app_type] => utility [patent_app_number] => 11/224332 [patent_app_country] => US [patent_app_date] => 2005-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3330 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20070239814.pdf [firstpage_image] =>[orig_patent_app_number] => 11224332 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/224332
Statistical control of adaptive ocular filter stability Sep 11, 2005 Issued
Array ( [id] => 301508 [patent_doc_number] => 07539717 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Logarithm processing systems and methods' [patent_app_type] => utility [patent_app_number] => 11/223289 [patent_app_country] => US [patent_app_date] => 2005-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6859 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/539/07539717.pdf [firstpage_image] =>[orig_patent_app_number] => 11223289 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/223289
Logarithm processing systems and methods Sep 8, 2005 Issued
Array ( [id] => 116099 [patent_doc_number] => 07720900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-18 [patent_title] => 'Fused multiply add split for multiple precision arithmetic' [patent_app_type] => utility [patent_app_number] => 11/223641 [patent_app_country] => US [patent_app_date] => 2005-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5565 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/720/07720900.pdf [firstpage_image] =>[orig_patent_app_number] => 11223641 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/223641
Fused multiply add split for multiple precision arithmetic Sep 8, 2005 Issued
Array ( [id] => 234545 [patent_doc_number] => 07599982 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-10-06 [patent_title] => 'Efficient hardware divide operation' [patent_app_type] => utility [patent_app_number] => 11/223837 [patent_app_country] => US [patent_app_date] => 2005-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5011 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/599/07599982.pdf [firstpage_image] =>[orig_patent_app_number] => 11223837 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/223837
Efficient hardware divide operation Sep 7, 2005 Issued
Array ( [id] => 234543 [patent_doc_number] => 07599980 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-10-06 [patent_title] => 'Efficient hardware square-root operation' [patent_app_type] => utility [patent_app_number] => 11/223836 [patent_app_country] => US [patent_app_date] => 2005-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4463 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/599/07599980.pdf [firstpage_image] =>[orig_patent_app_number] => 11223836 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/223836
Efficient hardware square-root operation Sep 7, 2005 Issued
Array ( [id] => 57698 [patent_doc_number] => 07774395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Digital filter for transmission-end pulse shaping' [patent_app_type] => utility [patent_app_number] => 11/217938 [patent_app_country] => US [patent_app_date] => 2005-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 8131 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/774/07774395.pdf [firstpage_image] =>[orig_patent_app_number] => 11217938 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/217938
Digital filter for transmission-end pulse shaping Aug 31, 2005 Issued
Array ( [id] => 592370 [patent_doc_number] => 07461108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-02 [patent_title] => 'Barrel shift device' [patent_app_type] => utility [patent_app_number] => 10/578780 [patent_app_country] => US [patent_app_date] => 2005-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8648 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/461/07461108.pdf [firstpage_image] =>[orig_patent_app_number] => 10578780 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/578780
Barrel shift device Aug 30, 2005 Issued
Array ( [id] => 268467 [patent_doc_number] => 07567996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-28 [patent_title] => 'Vector SIMD processor' [patent_app_type] => utility [patent_app_number] => 11/212736 [patent_app_country] => US [patent_app_date] => 2005-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 7843 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/567/07567996.pdf [firstpage_image] =>[orig_patent_app_number] => 11212736 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/212736
Vector SIMD processor Aug 28, 2005 Issued
Array ( [id] => 5891623 [patent_doc_number] => 20060277237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-07 [patent_title] => 'Nonlinear conversion system using precision mapping and the method thereof' [patent_app_type] => utility [patent_app_number] => 11/207783 [patent_app_country] => US [patent_app_date] => 2005-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3110 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20060277237.pdf [firstpage_image] =>[orig_patent_app_number] => 11207783 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/207783
Nonlinear conversion system using precision mapping and the method thereof Aug 21, 2005 Issued
Array ( [id] => 5001162 [patent_doc_number] => 20070043796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Residue-based error detection for a shift operation' [patent_app_type] => utility [patent_app_number] => 11/209124 [patent_app_country] => US [patent_app_date] => 2005-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5522 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20070043796.pdf [firstpage_image] =>[orig_patent_app_number] => 11209124 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/209124
Residue-based error detection for a shift operation Aug 21, 2005 Issued
Array ( [id] => 5001166 [patent_doc_number] => 20070043800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Reducing Computational Complexity in Determining the Distance From Each of a Set of Input Points to Each of a Set of Fixed Points' [patent_app_type] => utility [patent_app_number] => 11/161843 [patent_app_country] => US [patent_app_date] => 2005-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4321 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20070043800.pdf [firstpage_image] =>[orig_patent_app_number] => 11161843 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/161843
Reducing computational complexity in determining the distance from each of a set of input points to each of a set of fixed points Aug 17, 2005 Issued
Array ( [id] => 5001165 [patent_doc_number] => 20070043799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'System and method for generating a fixed point approximation to nonlinear functions' [patent_app_type] => utility [patent_app_number] => 11/207024 [patent_app_country] => US [patent_app_date] => 2005-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4833 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20070043799.pdf [firstpage_image] =>[orig_patent_app_number] => 11207024 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/207024
System and method for generating a fixed point approximation to nonlinear functions Aug 16, 2005 Issued
Array ( [id] => 5803434 [patent_doc_number] => 20060036835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'DSP processor architecture with write Datapath word conditioning and analysis' [patent_app_type] => utility [patent_app_number] => 11/201945 [patent_app_country] => US [patent_app_date] => 2005-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3108 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20060036835.pdf [firstpage_image] =>[orig_patent_app_number] => 11201945 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/201945
DSP processor architecture with write datapath word conditioning and analysis Aug 9, 2005 Issued
Array ( [id] => 7236090 [patent_doc_number] => 20050270677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-08 [patent_title] => 'Write compensation circuit and signal interpolation circuit of recording device' [patent_app_type] => utility [patent_app_number] => 11/198950 [patent_app_country] => US [patent_app_date] => 2005-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11856 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20050270677.pdf [firstpage_image] =>[orig_patent_app_number] => 11198950 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/198950
Write compensation circuit and signal interpolation circuit of recording device Aug 7, 2005 Issued
Array ( [id] => 5206462 [patent_doc_number] => 20070027944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'Instruction based parallel median filtering processor and method' [patent_app_type] => utility [patent_app_number] => 11/191513 [patent_app_country] => US [patent_app_date] => 2005-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3847 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20070027944.pdf [firstpage_image] =>[orig_patent_app_number] => 11191513 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/191513
Instruction based parallel median filtering processor and method Jul 27, 2005 Abandoned
11/191734 Discrete-time analytical signal generation system and method Jul 27, 2005 Abandoned
Array ( [id] => 7240080 [patent_doc_number] => 20050256917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'Address generators integrated with parallel FFT for mapping arrays in bit reversed order' [patent_app_type] => utility [patent_app_number] => 11/187673 [patent_app_country] => US [patent_app_date] => 2005-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12017 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20050256917.pdf [firstpage_image] =>[orig_patent_app_number] => 11187673 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/187673
Address generators integrated with parallel FFT for mapping arrays in bit reversed order Jul 21, 2005 Abandoned
Array ( [id] => 5132400 [patent_doc_number] => 20070208797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-06 [patent_title] => 'Single-Level Parallel-Gated Carry/majority Circuits and Systems Therefrom' [patent_app_type] => utility [patent_app_number] => 10/593807 [patent_app_country] => US [patent_app_date] => 2005-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20070208797.pdf [firstpage_image] =>[orig_patent_app_number] => 10593807 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/593807
Single-level parallel-gated carry/majority circuits and systems therefrom Jul 5, 2005 Issued
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