Search

Tan V. Mai

Examiner (ID: 15743)

Most Active Art Unit
2193
Art Unit(s)
2306, 2193, 2787, 2786, 2121, 2124, 2302, 2301, 2182, 2183
Total Applications
3863
Issued Applications
3431
Pending Applications
94
Abandoned Applications
349

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5915105 [patent_doc_number] => 20060129410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Frequency estimation' [patent_app_type] => utility [patent_app_number] => 10/520450 [patent_app_country] => US [patent_app_date] => 2003-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8500 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20060129410.pdf [firstpage_image] =>[orig_patent_app_number] => 10520450 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/520450
Frequency estimation Jul 3, 2003 Abandoned
Array ( [id] => 7603705 [patent_doc_number] => 07117233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-03 [patent_title] => 'Random number generator and method for generating a random number' [patent_app_type] => utility [patent_app_number] => 10/611065 [patent_app_country] => US [patent_app_date] => 2003-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4700 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/117/07117233.pdf [firstpage_image] =>[orig_patent_app_number] => 10611065 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/611065
Random number generator and method for generating a random number Jun 30, 2003 Issued
Array ( [id] => 805935 [patent_doc_number] => 07424501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-09 [patent_title] => 'Nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations' [patent_app_type] => utility [patent_app_number] => 10/610665 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 15581 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/424/07424501.pdf [firstpage_image] =>[orig_patent_app_number] => 10610665 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/610665
Nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations Jun 29, 2003 Issued
Array ( [id] => 7290439 [patent_doc_number] => 20040148323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Multi-dimensional hybrid and transpose form finite impulse response filters' [patent_app_type] => new [patent_app_number] => 10/610336 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2743 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20040148323.pdf [firstpage_image] =>[orig_patent_app_number] => 10610336 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/610336
Multi-dimensional hybrid and transpose form finite impulse response filters Jun 29, 2003 Issued
Array ( [id] => 7446947 [patent_doc_number] => 20040267854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Logarithmic and inverse logarithmic conversion system and method' [patent_app_type] => new [patent_app_number] => 10/606505 [patent_app_country] => US [patent_app_date] => 2003-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9998 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20040267854.pdf [firstpage_image] =>[orig_patent_app_number] => 10606505 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/606505
Logarithmic and inverse logarithmic conversion system and method Jun 25, 2003 Abandoned
Array ( [id] => 839666 [patent_doc_number] => 07395299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-01 [patent_title] => 'System and method for efficient hardware implementation of a perfect precision blending function' [patent_app_type] => utility [patent_app_number] => 10/602248 [patent_app_country] => US [patent_app_date] => 2003-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6849 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/395/07395299.pdf [firstpage_image] =>[orig_patent_app_number] => 10602248 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/602248
System and method for efficient hardware implementation of a perfect precision blending function Jun 22, 2003 Issued
Array ( [id] => 7447029 [patent_doc_number] => 20040267862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Adder including generate and propagate bits corresponding to multiple columns' [patent_app_type] => new [patent_app_number] => 10/601376 [patent_app_country] => US [patent_app_date] => 2003-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5965 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20040267862.pdf [firstpage_image] =>[orig_patent_app_number] => 10601376 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/601376
Adder including generate and propagate bits corresponding to multiple columns Jun 22, 2003 Issued
Array ( [id] => 336433 [patent_doc_number] => 07509362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Non-linear function approximation using finite order polynomial in fixed-point arithmetic' [patent_app_type] => utility [patent_app_number] => 10/464626 [patent_app_country] => US [patent_app_date] => 2003-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5542 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/509/07509362.pdf [firstpage_image] =>[orig_patent_app_number] => 10464626 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/464626
Non-linear function approximation using finite order polynomial in fixed-point arithmetic Jun 17, 2003 Issued
Array ( [id] => 7332863 [patent_doc_number] => 20040254971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Method and system for computing alignment sticky bit in floating-point operations' [patent_app_type] => new [patent_app_number] => 10/458946 [patent_app_country] => US [patent_app_date] => 2003-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6373 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20040254971.pdf [firstpage_image] =>[orig_patent_app_number] => 10458946 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/458946
Method and system for computing alignment sticky bit in floating-point operations Jun 10, 2003 Issued
Array ( [id] => 350494 [patent_doc_number] => 07496619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'System and methods of nonuniform data sampling and data reconstruction in shift invariant and wavelet spaces' [patent_app_type] => utility [patent_app_number] => 10/458475 [patent_app_country] => US [patent_app_date] => 2003-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 27393 [patent_no_of_claims] => 114 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/496/07496619.pdf [firstpage_image] =>[orig_patent_app_number] => 10458475 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/458475
System and methods of nonuniform data sampling and data reconstruction in shift invariant and wavelet spaces Jun 9, 2003 Issued
Array ( [id] => 507584 [patent_doc_number] => 07209940 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-04-24 [patent_title] => 'Temperature compensated square function generator' [patent_app_type] => utility [patent_app_number] => 10/458970 [patent_app_country] => US [patent_app_date] => 2003-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3574 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/209/07209940.pdf [firstpage_image] =>[orig_patent_app_number] => 10458970 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/458970
Temperature compensated square function generator Jun 9, 2003 Issued
Array ( [id] => 7140396 [patent_doc_number] => 20050182812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Aes mixcolumn transform' [patent_app_type] => utility [patent_app_number] => 10/516846 [patent_app_country] => US [patent_app_date] => 2003-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2767 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20050182812.pdf [firstpage_image] =>[orig_patent_app_number] => 10516846 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/516846
Logic circuit and method for performing AES MixColumn transform Jun 3, 2003 Issued
Array ( [id] => 7343075 [patent_doc_number] => 20040246955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Method and process for determining a quotient' [patent_app_type] => new [patent_app_number] => 10/454790 [patent_app_country] => US [patent_app_date] => 2003-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5374 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20040246955.pdf [firstpage_image] =>[orig_patent_app_number] => 10454790 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/454790
Method and process for determining a quotient Jun 2, 2003 Issued
Array ( [id] => 7261351 [patent_doc_number] => 20040260738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Sparse echo canceller' [patent_app_type] => new [patent_app_number] => 10/444265 [patent_app_country] => US [patent_app_date] => 2003-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4330 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20040260738.pdf [firstpage_image] =>[orig_patent_app_number] => 10444265 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/444265
Sparse echo canceller May 22, 2003 Issued
Array ( [id] => 7393059 [patent_doc_number] => 20040030736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Processing architecture for a reconfigurable arithmetic node' [patent_app_type] => new [patent_app_number] => 10/443596 [patent_app_country] => US [patent_app_date] => 2003-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 2962 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20040030736.pdf [firstpage_image] =>[orig_patent_app_number] => 10443596 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/443596
Processing architecture for a reconfigurable arithmetic node May 20, 2003 Issued
Array ( [id] => 6831277 [patent_doc_number] => 20030182335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Efficient interpolator for high speed timing recovery' [patent_app_type] => new [patent_app_number] => 10/439401 [patent_app_country] => US [patent_app_date] => 2003-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5142 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20030182335.pdf [firstpage_image] =>[orig_patent_app_number] => 10439401 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/439401
Efficient interpolator for high speed timing recovery May 15, 2003 Issued
Array ( [id] => 7432581 [patent_doc_number] => 20040230419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'DRAM access for MDCT/IDMCT implementation' [patent_app_type] => new [patent_app_number] => 10/439613 [patent_app_country] => US [patent_app_date] => 2003-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4203 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20040230419.pdf [firstpage_image] =>[orig_patent_app_number] => 10439613 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/439613
DRAM access for MDCT/IDMCT implementation May 14, 2003 Abandoned
Array ( [id] => 434742 [patent_doc_number] => 07266580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-04 [patent_title] => 'Modular binary multiplier for signed and unsigned operands of variable widths' [patent_app_type] => utility [patent_app_number] => 10/435976 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11142 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/266/07266580.pdf [firstpage_image] =>[orig_patent_app_number] => 10435976 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/435976
Modular binary multiplier for signed and unsigned operands of variable widths May 11, 2003 Issued
Array ( [id] => 562182 [patent_doc_number] => 07167886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-23 [patent_title] => 'Method for constructing logic circuits of small depth and complexity for operation of inversion in finite fields of characteristic 2' [patent_app_type] => utility [patent_app_number] => 10/430446 [patent_app_country] => US [patent_app_date] => 2003-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 8565 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/167/07167886.pdf [firstpage_image] =>[orig_patent_app_number] => 10430446 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/430446
Method for constructing logic circuits of small depth and complexity for operation of inversion in finite fields of characteristic 2 May 5, 2003 Issued
Array ( [id] => 7320964 [patent_doc_number] => 20040225706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'Parallel prefix networks that make tradeoffs between logic levels, fanout and wiring racks' [patent_app_type] => new [patent_app_number] => 10/431036 [patent_app_country] => US [patent_app_date] => 2003-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4063 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20040225706.pdf [firstpage_image] =>[orig_patent_app_number] => 10431036 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/431036
Parallel prefix networks that make tradeoffs between logic levels, fanout and wiring racks May 4, 2003 Issued
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