Search

Tan V. Mai

Examiner (ID: 15743)

Most Active Art Unit
2193
Art Unit(s)
2306, 2193, 2787, 2786, 2121, 2124, 2302, 2301, 2182, 2183
Total Applications
3863
Issued Applications
3431
Pending Applications
94
Abandoned Applications
349

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 839650 [patent_doc_number] => 07395296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-01 [patent_title] => 'Circuitry and method for performing non-arithmetic operations' [patent_app_type] => utility [patent_app_number] => 10/291861 [patent_app_country] => US [patent_app_date] => 2002-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3453 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/395/07395296.pdf [firstpage_image] =>[orig_patent_app_number] => 10291861 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/291861
Circuitry and method for performing non-arithmetic operations Nov 7, 2002 Issued
Array ( [id] => 552534 [patent_doc_number] => 07174357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-06 [patent_title] => 'Circuitry for carrying out division and/or square root operations requiring a plurality of iterations' [patent_app_type] => utility [patent_app_number] => 10/291850 [patent_app_country] => US [patent_app_date] => 2002-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 33 [patent_no_of_words] => 14708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/174/07174357.pdf [firstpage_image] =>[orig_patent_app_number] => 10291850 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/291850
Circuitry for carrying out division and/or square root operations requiring a plurality of iterations Nov 7, 2002 Issued
Array ( [id] => 6791243 [patent_doc_number] => 20030086587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-08 [patent_title] => 'Watermark detection' [patent_app_type] => new [patent_app_number] => 10/291009 [patent_app_country] => US [patent_app_date] => 2002-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3201 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20030086587.pdf [firstpage_image] =>[orig_patent_app_number] => 10291009 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/291009
Watermark detection Nov 7, 2002 Issued
Array ( [id] => 7603703 [patent_doc_number] => 07117235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-03 [patent_title] => 'Digital decimation filter having finite impulse response (FIR) decimation stages' [patent_app_type] => utility [patent_app_number] => 10/289485 [patent_app_country] => US [patent_app_date] => 2002-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3045 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/117/07117235.pdf [firstpage_image] =>[orig_patent_app_number] => 10289485 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/289485
Digital decimation filter having finite impulse response (FIR) decimation stages Nov 5, 2002 Issued
Array ( [id] => 580022 [patent_doc_number] => 07472147 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-30 [patent_title] => 'Random number string output apparatus, random number string output method, program, and information recording medium' [patent_app_type] => utility [patent_app_number] => 10/494792 [patent_app_country] => US [patent_app_date] => 2002-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3260 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/472/07472147.pdf [firstpage_image] =>[orig_patent_app_number] => 10494792 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/494792
Random number string output apparatus, random number string output method, program, and information recording medium Nov 4, 2002 Issued
Array ( [id] => 748962 [patent_doc_number] => 07031995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'Method and device for modulo calculation' [patent_app_type] => utility [patent_app_number] => 10/288215 [patent_app_country] => US [patent_app_date] => 2002-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3842 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/031/07031995.pdf [firstpage_image] =>[orig_patent_app_number] => 10288215 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/288215
Method and device for modulo calculation Nov 4, 2002 Issued
Array ( [id] => 493299 [patent_doc_number] => 07219118 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'SIMD addition circuit' [patent_app_type] => utility [patent_app_number] => 10/283246 [patent_app_country] => US [patent_app_date] => 2002-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4460 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/219/07219118.pdf [firstpage_image] =>[orig_patent_app_number] => 10283246 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/283246
SIMD addition circuit Oct 29, 2002 Issued
Array ( [id] => 7391091 [patent_doc_number] => 20040083247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Graph paper mode for a computer device' [patent_app_type] => new [patent_app_number] => 10/282565 [patent_app_country] => US [patent_app_date] => 2002-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1938 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20040083247.pdf [firstpage_image] =>[orig_patent_app_number] => 10282565 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/282565
Graph paper mode for a computer device Oct 28, 2002 Abandoned
Array ( [id] => 645380 [patent_doc_number] => 07124162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Adder tree structure digital signal processor system and method' [patent_app_type] => utility [patent_app_number] => 10/282523 [patent_app_country] => US [patent_app_date] => 2002-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3269 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/124/07124162.pdf [firstpage_image] =>[orig_patent_app_number] => 10282523 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/282523
Adder tree structure digital signal processor system and method Oct 28, 2002 Issued
Array ( [id] => 764710 [patent_doc_number] => 07016930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Apparatus and method for performing operations implemented by iterative execution of a recurrence equation' [patent_app_type] => utility [patent_app_number] => 10/280095 [patent_app_country] => US [patent_app_date] => 2002-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10657 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/016/07016930.pdf [firstpage_image] =>[orig_patent_app_number] => 10280095 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/280095
Apparatus and method for performing operations implemented by iterative execution of a recurrence equation Oct 24, 2002 Issued
Array ( [id] => 7215603 [patent_doc_number] => 20040088610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'Apparatus for processing signal using minimum mean square error algorithm' [patent_app_type] => new [patent_app_number] => 10/279962 [patent_app_country] => US [patent_app_date] => 2002-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8916 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20040088610.pdf [firstpage_image] =>[orig_patent_app_number] => 10279962 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/279962
Apparatus for processing signal using minimum mean square error algorithm Oct 23, 2002 Abandoned
Array ( [id] => 860107 [patent_doc_number] => 07376690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-20 [patent_title] => 'Time discrete filter comprising upsampling, sampling rate conversion and downsampling stages' [patent_app_type] => utility [patent_app_number] => 10/495583 [patent_app_country] => US [patent_app_date] => 2002-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3175 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/376/07376690.pdf [firstpage_image] =>[orig_patent_app_number] => 10495583 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/495583
Time discrete filter comprising upsampling, sampling rate conversion and downsampling stages Oct 23, 2002 Issued
Array ( [id] => 6793254 [patent_doc_number] => 20030088598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-08 [patent_title] => 'Filter processing apparatus and method' [patent_app_type] => new [patent_app_number] => 10/278941 [patent_app_country] => US [patent_app_date] => 2002-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 14241 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20030088598.pdf [firstpage_image] =>[orig_patent_app_number] => 10278941 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/278941
Filter processing apparatus and method Oct 23, 2002 Issued
Array ( [id] => 533266 [patent_doc_number] => 07194501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'Complementary pass gate logic implementation of 64-bit arithmetic logic unit using propagate, generate, and kill' [patent_app_type] => utility [patent_app_number] => 10/278440 [patent_app_country] => US [patent_app_date] => 2002-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 11485 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/194/07194501.pdf [firstpage_image] =>[orig_patent_app_number] => 10278440 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/278440
Complementary pass gate logic implementation of 64-bit arithmetic logic unit using propagate, generate, and kill Oct 21, 2002 Issued
Array ( [id] => 666612 [patent_doc_number] => 07103620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Method and apparatus for verification of digital arithmetic circuits by means of an equivalence comparison' [patent_app_type] => utility [patent_app_number] => 10/277700 [patent_app_country] => US [patent_app_date] => 2002-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2169 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/103/07103620.pdf [firstpage_image] =>[orig_patent_app_number] => 10277700 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/277700
Method and apparatus for verification of digital arithmetic circuits by means of an equivalence comparison Oct 21, 2002 Issued
Array ( [id] => 610697 [patent_doc_number] => 07152085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-19 [patent_title] => 'Non-phase shifting bidimensional filter' [patent_app_type] => utility [patent_app_number] => 10/273742 [patent_app_country] => US [patent_app_date] => 2002-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1607 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/152/07152085.pdf [firstpage_image] =>[orig_patent_app_number] => 10273742 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/273742
Non-phase shifting bidimensional filter Oct 17, 2002 Issued
Array ( [id] => 7173428 [patent_doc_number] => 20040078408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Modular galois-field subfield-power integrated inverter-multiplier circuit for galois-field division over GF(256)' [patent_app_type] => new [patent_app_number] => 10/273002 [patent_app_country] => US [patent_app_date] => 2002-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9449 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20040078408.pdf [firstpage_image] =>[orig_patent_app_number] => 10273002 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/273002
Modular Galois-field subfield-power integrated inverter-multiplier circuit for Galois-field division over GF(256) Oct 17, 2002 Issued
Array ( [id] => 658987 [patent_doc_number] => 07111027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-19 [patent_title] => 'Method for automatically adding scale symbol to operation formula during operation and system executing the method' [patent_app_type] => utility [patent_app_number] => 10/271731 [patent_app_country] => US [patent_app_date] => 2002-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1726 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/111/07111027.pdf [firstpage_image] =>[orig_patent_app_number] => 10271731 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/271731
Method for automatically adding scale symbol to operation formula during operation and system executing the method Oct 16, 2002 Issued
Array ( [id] => 523536 [patent_doc_number] => 07197527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-27 [patent_title] => 'Efficient arithmetic in finite fields of odd characteristic on binary hardware' [patent_app_type] => utility [patent_app_number] => 10/271730 [patent_app_country] => US [patent_app_date] => 2002-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 34 [patent_no_of_words] => 50580 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/197/07197527.pdf [firstpage_image] =>[orig_patent_app_number] => 10271730 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/271730
Efficient arithmetic in finite fields of odd characteristic on binary hardware Oct 16, 2002 Issued
Array ( [id] => 658997 [patent_doc_number] => 07111031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-19 [patent_title] => 'Dual processor having a function calculating the sum of the results of a plurality of arithmetic operations' [patent_app_type] => utility [patent_app_number] => 10/271771 [patent_app_country] => US [patent_app_date] => 2002-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 8917 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/111/07111031.pdf [firstpage_image] =>[orig_patent_app_number] => 10271771 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/271771
Dual processor having a function calculating the sum of the results of a plurality of arithmetic operations Oct 16, 2002 Issued
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