Search

Tan V. Mai

Examiner (ID: 15743)

Most Active Art Unit
2193
Art Unit(s)
2306, 2193, 2787, 2786, 2121, 2124, 2302, 2301, 2182, 2183
Total Applications
3863
Issued Applications
3431
Pending Applications
94
Abandoned Applications
349

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 615524 [patent_doc_number] => 07149768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-12 [patent_title] => '3-input arithmetic logic unit' [patent_app_type] => utility [patent_app_number] => 10/271901 [patent_app_country] => US [patent_app_date] => 2002-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4333 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/149/07149768.pdf [firstpage_image] =>[orig_patent_app_number] => 10271901 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/271901
3-input arithmetic logic unit Oct 14, 2002 Issued
Array ( [id] => 771066 [patent_doc_number] => 07010562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Arithmetic circuit' [patent_app_type] => utility [patent_app_number] => 10/269856 [patent_app_country] => US [patent_app_date] => 2002-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4440 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/010/07010562.pdf [firstpage_image] =>[orig_patent_app_number] => 10269856 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/269856
Arithmetic circuit Oct 14, 2002 Issued
Array ( [id] => 7605816 [patent_doc_number] => 07099906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-29 [patent_title] => 'Random bit sequence generator' [patent_app_type] => utility [patent_app_number] => 10/270020 [patent_app_country] => US [patent_app_date] => 2002-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2055 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/099/07099906.pdf [firstpage_image] =>[orig_patent_app_number] => 10270020 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/270020
Random bit sequence generator Oct 10, 2002 Issued
Array ( [id] => 7232684 [patent_doc_number] => 20040073587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-15 [patent_title] => 'Systolic ring-planarized cylindrical array modular multipler' [patent_app_type] => new [patent_app_number] => 10/267605 [patent_app_country] => US [patent_app_date] => 2002-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1970 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 1318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20040073587.pdf [firstpage_image] =>[orig_patent_app_number] => 10267605 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/267605
Systolic ring-planarized cylindrical array modular multipler Oct 8, 2002 Issued
Array ( [id] => 7282115 [patent_doc_number] => 20040064492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Efficient reconstruction' [patent_app_type] => new [patent_app_number] => 10/259676 [patent_app_country] => US [patent_app_date] => 2002-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5330 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20040064492.pdf [firstpage_image] =>[orig_patent_app_number] => 10259676 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/259676
Efficient reconstruction Sep 26, 2002 Issued
Array ( [id] => 7232753 [patent_doc_number] => 20040073595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-15 [patent_title] => 'Non-reciprocal network element that produces an input impedance that is a function of the multiplication-division of its load impedances' [patent_app_type] => new [patent_app_number] => 10/260088 [patent_app_country] => US [patent_app_date] => 2002-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9001 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20040073595.pdf [firstpage_image] =>[orig_patent_app_number] => 10260088 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/260088
Non-reciprocal network element that produces an input impedance that is a function of the multiplication-division of its load impedances Sep 26, 2002 Issued
Array ( [id] => 7282119 [patent_doc_number] => 20040064496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Non-reciprocal network element that produces an input impedance that is a product of its load impedances' [patent_app_type] => new [patent_app_number] => 10/260873 [patent_app_country] => US [patent_app_date] => 2002-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5746 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20040064496.pdf [firstpage_image] =>[orig_patent_app_number] => 10260873 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/260873
Non-reciprocal network element that produces an input impedance that is a product of its load impedances Sep 26, 2002 Issued
Array ( [id] => 6746466 [patent_doc_number] => 20030023649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Digital filtering method and device and sound image localizing device' [patent_app_type] => new [patent_app_number] => 10/254403 [patent_app_country] => US [patent_app_date] => 2002-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9474 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20030023649.pdf [firstpage_image] =>[orig_patent_app_number] => 10254403 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/254403
Digital filtering method and device and sound image localizing device Sep 24, 2002 Issued
Array ( [id] => 6852822 [patent_doc_number] => 20030145025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-31 [patent_title] => 'Method of designing families of boost and cut filters, including treble and bass controls and graphic equalizers' [patent_app_type] => new [patent_app_number] => 10/253676 [patent_app_country] => US [patent_app_date] => 2002-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5517 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20030145025.pdf [firstpage_image] =>[orig_patent_app_number] => 10253676 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/253676
Method of designing families of boost and cut filters, including treble and bass controls and graphic equalizers Sep 23, 2002 Abandoned
Array ( [id] => 626161 [patent_doc_number] => 07139789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-21 [patent_title] => 'Adder increment circuit' [patent_app_type] => utility [patent_app_number] => 10/252045 [patent_app_country] => US [patent_app_date] => 2002-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 8180 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/139/07139789.pdf [firstpage_image] =>[orig_patent_app_number] => 10252045 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/252045
Adder increment circuit Sep 22, 2002 Issued
Array ( [id] => 7082288 [patent_doc_number] => 20050047668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Method and arrangement for signal processing particular image signal processing' [patent_app_type] => utility [patent_app_number] => 10/490352 [patent_app_country] => US [patent_app_date] => 2002-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2068 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20050047668.pdf [firstpage_image] =>[orig_patent_app_number] => 10490352 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/490352
Method and arrangement for signal processing particular image signal processing Sep 19, 2002 Abandoned
Array ( [id] => 6746469 [patent_doc_number] => 20030023652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Circuit and method for computing a fast fourier transform' [patent_app_type] => new [patent_app_number] => 10/247144 [patent_app_country] => US [patent_app_date] => 2002-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5621 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20030023652.pdf [firstpage_image] =>[orig_patent_app_number] => 10247144 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/247144
Circuit and method for computing a fast fourier transform Sep 18, 2002 Issued
Array ( [id] => 7603700 [patent_doc_number] => 07117238 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-03 [patent_title] => 'Method and system for performing pipelined reciprocal and reciprocal square root operations' [patent_app_type] => utility [patent_app_number] => 10/247115 [patent_app_country] => US [patent_app_date] => 2002-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10574 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/117/07117238.pdf [firstpage_image] =>[orig_patent_app_number] => 10247115 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/247115
Method and system for performing pipelined reciprocal and reciprocal square root operations Sep 18, 2002 Issued
Array ( [id] => 685315 [patent_doc_number] => 07082451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-25 [patent_title] => 'Reconfigurable vector-FFT/IFFT, vector-multiplier/divider' [patent_app_type] => utility [patent_app_number] => 10/237465 [patent_app_country] => US [patent_app_date] => 2002-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 5304 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/082/07082451.pdf [firstpage_image] =>[orig_patent_app_number] => 10237465 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/237465
Reconfigurable vector-FFT/IFFT, vector-multiplier/divider Sep 8, 2002 Issued
Array ( [id] => 6698003 [patent_doc_number] => 20030110197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'System and method to implement a matrix multiply unit of a broadband processor' [patent_app_type] => new [patent_app_number] => 10/233779 [patent_app_country] => US [patent_app_date] => 2002-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5311 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20030110197.pdf [firstpage_image] =>[orig_patent_app_number] => 10233779 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/233779
System and method to implement a matrix multiply unit of a broadband processor Sep 3, 2002 Issued
Array ( [id] => 6746465 [patent_doc_number] => 20030023648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Method and apparatus for producing pseudorandom signal' [patent_app_type] => new [patent_app_number] => 10/233795 [patent_app_country] => US [patent_app_date] => 2002-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3433 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20030023648.pdf [firstpage_image] =>[orig_patent_app_number] => 10233795 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/233795
Method and apparatus for producing pseudorandom signal Sep 2, 2002 Issued
Array ( [id] => 305318 [patent_doc_number] => 07536431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Vector-matrix multiplication' [patent_app_type] => utility [patent_app_number] => 10/488581 [patent_app_country] => US [patent_app_date] => 2002-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 32071 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/536/07536431.pdf [firstpage_image] =>[orig_patent_app_number] => 10488581 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/488581
Vector-matrix multiplication Sep 2, 2002 Issued
Array ( [id] => 7411266 [patent_doc_number] => 20040024806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Pipelined divider and dividing method with small lookup table' [patent_app_type] => new [patent_app_number] => 10/231566 [patent_app_country] => US [patent_app_date] => 2002-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6870 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20040024806.pdf [firstpage_image] =>[orig_patent_app_number] => 10231566 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/231566
Pipelined divider and dividing method with small lookup table Aug 29, 2002 Issued
Array ( [id] => 6779863 [patent_doc_number] => 20030050945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-13 [patent_title] => 'RAM-based fast fourier transform unit for wireless communications' [patent_app_type] => new [patent_app_number] => 10/234060 [patent_app_country] => US [patent_app_date] => 2002-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5933 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20030050945.pdf [firstpage_image] =>[orig_patent_app_number] => 10234060 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/234060
RAM-based fast fourier transform unit for wireless communications Aug 29, 2002 Issued
Array ( [id] => 6693651 [patent_doc_number] => 20030041083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'Method and apparatus for high speed calculation of non-linear functions and networks using non-linear function calculations for digital signal processing' [patent_app_type] => new [patent_app_number] => 10/226735 [patent_app_country] => US [patent_app_date] => 2002-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10864 [patent_no_of_claims] => 77 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20030041083.pdf [firstpage_image] =>[orig_patent_app_number] => 10226735 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/226735
Method and apparatus for high speed calculation of non-linear functions and networks using non-linear function calculations for digital signal processing Aug 21, 2002 Issued
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