Tanh Q. Nguyen

Array ( [id] => 6580157 [patent_doc_number] => 20020166038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-07 [patent_title] => 'Caching for I/O virtual address translation and validation using device drivers' [patent_app_type] => new [patent_app_number] => 09/789051 [patent_app_country] => US [patent_app_date] => 2001-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5851 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20020166038.pdf [firstpage_image] =>[orig_patent_app_number] => 09789051 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6565238 [patent_doc_number] => 20020112105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-15 [patent_title] => 'Method and apparatus for efficient messaging between memories across a PCI bus' [patent_app_type] => new [patent_app_number] => 09/782090 [patent_app_country] => US [patent_app_date] => 2001-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4542 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20020112105.pdf [firstpage_image] =>[orig_patent_app_number] => 09782090 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1124702 [patent_doc_number] => 06799225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-28 [patent_title] => 'Controllerless modem' [patent_app_type] => B2 [patent_app_number] => 09/778511 [patent_app_country] => US [patent_app_date] => 2001-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 14733 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/799/06799225.pdf [firstpage_image] =>[orig_patent_app_number] => 09778511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7384475 [patent_doc_number] => 20040221071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'INTEGRATED MULTIMEDIA SYSTEM' [patent_app_type] => new [patent_app_number] => 09/777003 [patent_app_country] => US [patent_app_date] => 2001-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 29035 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20040221071.pdf [firstpage_image] =>[orig_patent_app_number] => 09777003 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5791416 [patent_doc_number] => 20020161942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'Information processing apparatus and method and recording medium' [patent_app_type] => new [patent_app_number] => 09/913688 [patent_app_country] => US [patent_app_date] => 2001-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7637 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20020161942.pdf [firstpage_image] =>[orig_patent_app_number] => 09913688 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5970222 [patent_doc_number] => 20020091532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'System and method for controlling access to documents stored on an internal network' [patent_app_type] => new [patent_app_number] => 09/728775 [patent_app_country] => US [patent_app_date] => 2000-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9189 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20020091532.pdf [firstpage_image] =>[orig_patent_app_number] => 09728775 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1360888 [patent_doc_number] => 06587894 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Apparatus for detecting data collision on data bus for out-of-order memory accesses with access execution time based in part on characterization data specific to memory' [patent_app_type] => B1 [patent_app_number] => 09/712993 [patent_app_country] => US [patent_app_date] => 2000-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 37 [patent_no_of_words] => 15489 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/587/06587894.pdf [firstpage_image] =>[orig_patent_app_number] => 09712993 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1234194 [patent_doc_number] => 06697895 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-24 [patent_title] => 'Network attached tape storage system' [patent_app_type] => B1 [patent_app_number] => 09/710013 [patent_app_country] => US [patent_app_date] => 2000-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7790 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697895.pdf [firstpage_image] =>[orig_patent_app_number] => 09710013 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1592253 [patent_doc_number] => 06360286 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Sequential data transfer with common clock signal for receiver and sequential storage device and with slack register storing overflow item when set-up time is insufficient' [patent_app_type] => B1 [patent_app_number] => 09/705227 [patent_app_country] => US [patent_app_date] => 2000-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4895 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/360/06360286.pdf [firstpage_image] =>[orig_patent_app_number] => 09705227 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1338678 [patent_doc_number] => RE038134 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2003-06-03 [patent_title] => 'System for communications where first priority data transfer is not disturbed by second priority data transfer and where allocated bandwidth is removed when process terminates abnormally' [patent_app_type] => E1 [patent_app_number] => 09/679447 [patent_app_country] => US [patent_app_date] => 2000-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10502 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/038/RE038134.pdf [firstpage_image] =>[orig_patent_app_number] => 09679447 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1112086 [patent_doc_number] => 06810433 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-26 [patent_title] => 'Peripheral device for programmable controller' [patent_app_type] => B1 [patent_app_number] => 09/643954 [patent_app_country] => US [patent_app_date] => 2000-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8258 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/810/06810433.pdf [firstpage_image] =>[orig_patent_app_number] => 09643954 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4423173 [patent_doc_number] => 06311234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Direct memory access controller with split channel transfer capability and FIFO buffering' [patent_app_type] => 1 [patent_app_number] => 9/633998 [patent_app_country] => US [patent_app_date] => 2000-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 12059 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311234.pdf [firstpage_image] =>[orig_patent_app_number] => 633998 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1279394 [patent_doc_number] => 06654845 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'System and method implementing a secondary bus to avoid read data latency' [patent_app_type] => B1 [patent_app_number] => 09/610964 [patent_app_country] => US [patent_app_date] => 2000-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3397 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654845.pdf [firstpage_image] =>[orig_patent_app_number] => 09610964 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1138824 [patent_doc_number] => 06789138 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-07 [patent_title] => 'Computer peripheral apparatus and a computer readable medium having a program for controlling the computer peripheral apparatus' [patent_app_type] => B1 [patent_app_number] => 09/610290 [patent_app_country] => US [patent_app_date] => 2000-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5067 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/789/06789138.pdf [firstpage_image] =>[orig_patent_app_number] => 09610290 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7630030 [patent_doc_number] => 06636909 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Adaptive throttling for fiber channel disks' [patent_app_type] => B1 [patent_app_number] => 09/610847 [patent_app_country] => US [patent_app_date] => 2000-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 3476 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636909.pdf [firstpage_image] =>[orig_patent_app_number] => 09610847 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4423216 [patent_doc_number] => 06311238 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Telecommunication switch with layer-specific processor capable of attaching atomic function message buffer to internal representation of ppl event indication message upon occurrence of predetermined event' [patent_app_type] => 1 [patent_app_number] => 9/603367 [patent_app_country] => US [patent_app_date] => 2000-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12598 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311238.pdf [firstpage_image] =>[orig_patent_app_number] => 603367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1429056 [patent_doc_number] => 06529976 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Heterogeneous computer system, heterogeneous input output system and data back-up method for the systems' [patent_app_type] => B1 [patent_app_number] => 09/594012 [patent_app_country] => US [patent_app_date] => 2000-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5724 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529976.pdf [firstpage_image] =>[orig_patent_app_number] => 09594012 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1326650 [patent_doc_number] => 06609163 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-19 [patent_title] => 'Multi-channel serial port with programmable features' [patent_app_type] => B1 [patent_app_number] => 09/591527 [patent_app_country] => US [patent_app_date] => 2000-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 58 [patent_no_of_words] => 18646 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 400 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/609/06609163.pdf [firstpage_image] =>[orig_patent_app_number] => 09591527 [rel_patent_id] =>[rel_patent_doc_number] =>)