Search

Tanh Q. Nguyen

Examiner (ID: 1959, Phone: (571)272-4154 , Office: P/2118 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2187, 2782, 2116, 2118
Total Applications
709
Issued Applications
458
Pending Applications
29
Abandoned Applications
223

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7625758 [patent_doc_number] => 06769009 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-27 [patent_title] => 'Method and system for selecting a personalized set of information channels' [patent_app_type] => B1 [patent_app_number] => 09/553393 [patent_app_country] => US [patent_app_date] => 2000-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 33292 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/769/06769009.pdf [firstpage_image] =>[orig_patent_app_number] => 09553393 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/553393
Method and system for selecting a personalized set of information channels Apr 19, 2000 Issued
Array ( [id] => 1279340 [patent_doc_number] => 06654835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'High bandwidth data transfer employing a multi-mode, shared line buffer' [patent_app_type] => B1 [patent_app_number] => 09/535068 [patent_app_country] => US [patent_app_date] => 2000-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5806 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654835.pdf [firstpage_image] =>[orig_patent_app_number] => 09535068 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/535068
High bandwidth data transfer employing a multi-mode, shared line buffer Mar 22, 2000 Issued
Array ( [id] => 1143324 [patent_doc_number] => 06785743 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-31 [patent_title] => 'Template data transfer coprocessor' [patent_app_type] => B1 [patent_app_number] => 09/533047 [patent_app_country] => US [patent_app_date] => 2000-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 6068 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/785/06785743.pdf [firstpage_image] =>[orig_patent_app_number] => 09533047 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/533047
Template data transfer coprocessor Mar 21, 2000 Issued
Array ( [id] => 1291703 [patent_doc_number] => 06643721 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Input device-adaptive human-computer interface' [patent_app_type] => B1 [patent_app_number] => 09/533388 [patent_app_country] => US [patent_app_date] => 2000-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5590 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643721.pdf [firstpage_image] =>[orig_patent_app_number] => 09533388 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/533388
Input device-adaptive human-computer interface Mar 21, 2000 Issued
Array ( [id] => 1288868 [patent_doc_number] => 06647446 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-11 [patent_title] => 'Method and system for using a new bus identifier resulting from a bus topology change' [patent_app_type] => B1 [patent_app_number] => 09/531061 [patent_app_country] => US [patent_app_date] => 2000-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10723 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/647/06647446.pdf [firstpage_image] =>[orig_patent_app_number] => 09531061 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/531061
Method and system for using a new bus identifier resulting from a bus topology change Mar 17, 2000 Issued
Array ( [id] => 1573727 [patent_doc_number] => 06499077 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Bus interface unit for reflecting state information for a transfer request to a requesting device' [patent_app_type] => B1 [patent_app_number] => 09/475964 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5374 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/499/06499077.pdf [firstpage_image] =>[orig_patent_app_number] => 09475964 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475964
Bus interface unit for reflecting state information for a transfer request to a requesting device Dec 29, 1999 Issued
Array ( [id] => 609914 [patent_doc_number] => 07151298 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-12-19 [patent_title] => 'Electrostatic discharge protection network having distributed components' [patent_app_type] => utility [patent_app_number] => 09/468015 [patent_app_country] => US [patent_app_date] => 1999-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4892 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/151/07151298.pdf [firstpage_image] =>[orig_patent_app_number] => 09468015 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/468015
Electrostatic discharge protection network having distributed components Dec 19, 1999 Issued
Array ( [id] => 1567347 [patent_doc_number] => 06363444 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Slave processor to slave memory data transfer with master processor writing address to slave memory and providing control input to slave processor and slave memory' [patent_app_type] => B1 [patent_app_number] => 09/464626 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4555 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363444.pdf [firstpage_image] =>[orig_patent_app_number] => 09464626 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/464626
Slave processor to slave memory data transfer with master processor writing address to slave memory and providing control input to slave processor and slave memory Dec 16, 1999 Issued
Array ( [id] => 4294557 [patent_doc_number] => 06324614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Tap with scannable control circuit for selecting first test data register in tap or second test data register in tap linking module for scanning data' [patent_app_type] => 1 [patent_app_number] => 9/458313 [patent_app_country] => US [patent_app_date] => 1999-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 7044 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324614.pdf [firstpage_image] =>[orig_patent_app_number] => 458313 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/458313
Tap with scannable control circuit for selecting first test data register in tap or second test data register in tap linking module for scanning data Dec 9, 1999 Issued
Array ( [id] => 1423311 [patent_doc_number] => 06539440 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Methods and apparatus for prediction of the time between two consecutive memory accesses' [patent_app_type] => B1 [patent_app_number] => 09/439867 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 37 [patent_no_of_words] => 15289 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539440.pdf [firstpage_image] =>[orig_patent_app_number] => 09439867 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439867
Methods and apparatus for prediction of the time between two consecutive memory accesses Nov 11, 1999 Issued
Array ( [id] => 1429643 [patent_doc_number] => 06510474 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Methods and apparatus for re-reordering command and data packets in order to restore an original order of out-of-order memory requests' [patent_app_type] => B1 [patent_app_number] => 09/439866 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 36 [patent_no_of_words] => 15265 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510474.pdf [firstpage_image] =>[orig_patent_app_number] => 09439866 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439866
Methods and apparatus for re-reordering command and data packets in order to restore an original order of out-of-order memory requests Nov 11, 1999 Issued
Array ( [id] => 1416680 [patent_doc_number] => 06532505 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Universal resource access controller' [patent_app_type] => B1 [patent_app_number] => 09/439544 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 35 [patent_no_of_words] => 15296 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/532/06532505.pdf [firstpage_image] =>[orig_patent_app_number] => 09439544 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439544
Universal resource access controller Nov 11, 1999 Issued
Array ( [id] => 4370697 [patent_doc_number] => 06216178 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Methods and apparatus for detecting the collision of data on a data bus in case of out-of-order memory accesses of different times of memory access execution' [patent_app_type] => 1 [patent_app_number] => 9/439276 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 34 [patent_no_of_words] => 15679 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/216/06216178.pdf [firstpage_image] =>[orig_patent_app_number] => 439276 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439276
Methods and apparatus for detecting the collision of data on a data bus in case of out-of-order memory accesses of different times of memory access execution Nov 11, 1999 Issued
Array ( [id] => 1484907 [patent_doc_number] => 06453370 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Using of bank tag registers to avoid a background operation collision in memory systems' [patent_app_type] => B1 [patent_app_number] => 09/439591 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 37 [patent_no_of_words] => 15634 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453370.pdf [firstpage_image] =>[orig_patent_app_number] => 09439591 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439591
Using of bank tag registers to avoid a background operation collision in memory systems Nov 11, 1999 Issued
Array ( [id] => 4351733 [patent_doc_number] => 06314486 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Data transfer with JTAG controller using index register to specipy one of several control/status registers for access in read and write operations with data register' [patent_app_type] => 1 [patent_app_number] => 9/418623 [patent_app_country] => US [patent_app_date] => 1999-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2856 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314486.pdf [firstpage_image] =>[orig_patent_app_number] => 418623 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/418623
Data transfer with JTAG controller using index register to specipy one of several control/status registers for access in read and write operations with data register Oct 14, 1999 Issued
Array ( [id] => 1183438 [patent_doc_number] => 06751690 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-15 [patent_title] => 'Data converter with statistical domain output' [patent_app_type] => B1 [patent_app_number] => 09/416700 [patent_app_country] => US [patent_app_date] => 1999-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 37 [patent_no_of_words] => 18863 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751690.pdf [firstpage_image] =>[orig_patent_app_number] => 09416700 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/416700
Data converter with statistical domain output Oct 11, 1999 Issued
Array ( [id] => 1296950 [patent_doc_number] => 06633933 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Controller for ATAPI mode operation and ATAPI driven universal serial bus mode operation and methods for making the same' [patent_app_type] => B1 [patent_app_number] => 09/410172 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 12150 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633933.pdf [firstpage_image] =>[orig_patent_app_number] => 09410172 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/410172
Controller for ATAPI mode operation and ATAPI driven universal serial bus mode operation and methods for making the same Sep 29, 1999 Issued
Array ( [id] => 1177399 [patent_doc_number] => 06760799 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-06 [patent_title] => 'Reduced networking interrupts' [patent_app_type] => B1 [patent_app_number] => 09/409626 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5612 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760799.pdf [firstpage_image] =>[orig_patent_app_number] => 09409626 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/409626
Reduced networking interrupts Sep 29, 1999 Issued
Array ( [id] => 1431348 [patent_doc_number] => 06519660 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Method, system and program products for determining I/O configuration entropy' [patent_app_type] => B1 [patent_app_number] => 09/407453 [patent_app_country] => US [patent_app_date] => 1999-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 39 [patent_no_of_words] => 14920 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519660.pdf [firstpage_image] =>[orig_patent_app_number] => 09407453 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/407453
Method, system and program products for determining I/O configuration entropy Sep 27, 1999 Issued
Array ( [id] => 4291837 [patent_doc_number] => 06247073 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Memory outputting both data and timing signal with output data and timing signal being aligned with each other' [patent_app_type] => 1 [patent_app_number] => 9/400999 [patent_app_country] => US [patent_app_date] => 1999-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9572 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247073.pdf [firstpage_image] =>[orig_patent_app_number] => 400999 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/400999
Memory outputting both data and timing signal with output data and timing signal being aligned with each other Sep 20, 1999 Issued
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