| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 4401776
[patent_doc_number] => 06279050
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-21
[patent_title] => 'Data transfer apparatus having upper, lower, middle state machines, with middle state machine arbitrating among lower state machine side requesters including selective assembly/disassembly requests'
[patent_app_type] => 1
[patent_app_number] => 9/216329
[patent_app_country] => US
[patent_app_date] => 1998-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 41
[patent_no_of_words] => 29188
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/279/06279050.pdf
[firstpage_image] =>[orig_patent_app_number] => 216329
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/216329 | Data transfer apparatus having upper, lower, middle state machines, with middle state machine arbitrating among lower state machine side requesters including selective assembly/disassembly requests | Dec 17, 1998 | Issued |
Array
(
[id] => 4280552
[patent_doc_number] => 06260098
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-10
[patent_title] => 'Shared peripheral controller'
[patent_app_type] => 1
[patent_app_number] => 9/215023
[patent_app_country] => US
[patent_app_date] => 1998-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 6567
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/260/06260098.pdf
[firstpage_image] =>[orig_patent_app_number] => 215023
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/215023 | Shared peripheral controller | Dec 16, 1998 | Issued |
Array
(
[id] => 1557012
[patent_doc_number] => 06349304
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-19
[patent_title] => 'Graphical interface for copying settings from network source device to network target devices without transmitting values not usable for features supported by network target devices'
[patent_app_type] => B1
[patent_app_number] => 09/207810
[patent_app_country] => US
[patent_app_date] => 1998-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6611
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/349/06349304.pdf
[firstpage_image] =>[orig_patent_app_number] => 09207810
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/207810 | Graphical interface for copying settings from network source device to network target devices without transmitting values not usable for features supported by network target devices | Dec 8, 1998 | Issued |
Array
(
[id] => 4304514
[patent_doc_number] => 06269413
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-31
[patent_title] => 'System with multiple dynamically-sized logical FIFOs sharing single memory and with read/write pointers independently selectable and simultaneously responsive to respective read/write FIFO selections'
[patent_app_type] => 1
[patent_app_number] => 9/183705
[patent_app_country] => US
[patent_app_date] => 1998-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 6060
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/269/06269413.pdf
[firstpage_image] =>[orig_patent_app_number] => 183705
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/183705 | System with multiple dynamically-sized logical FIFOs sharing single memory and with read/write pointers independently selectable and simultaneously responsive to respective read/write FIFO selections | Oct 29, 1998 | Issued |
Array
(
[id] => 1324947
[patent_doc_number] => 06615294
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-02
[patent_title] => 'Recording/reproducing apparatus using an IC memory'
[patent_app_type] => B1
[patent_app_number] => 09/182792
[patent_app_country] => US
[patent_app_date] => 1998-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 6905
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 276
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/615/06615294.pdf
[firstpage_image] =>[orig_patent_app_number] => 09182792
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/182792 | Recording/reproducing apparatus using an IC memory | Oct 29, 1998 | Issued |
Array
(
[id] => 4273228
[patent_doc_number] => 06209043
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-27
[patent_title] => 'Command-controllable IC memory with compatibility checking unit suspending memory operation/enabling data to be only read from memory when IC memory operation is host incompatible'
[patent_app_type] => 1
[patent_app_number] => 9/182642
[patent_app_country] => US
[patent_app_date] => 1998-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 9280
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/209/06209043.pdf
[firstpage_image] =>[orig_patent_app_number] => 182642
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/182642 | Command-controllable IC memory with compatibility checking unit suspending memory operation/enabling data to be only read from memory when IC memory operation is host incompatible | Oct 29, 1998 | Issued |
Array
(
[id] => 1572218
[patent_doc_number] => 06378012
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-23
[patent_title] => 'Interface with data transmission mode from weighing scale to one or more peripheral devices and mailing machine tripping mode determined by individual peripheral device protocol'
[patent_app_type] => B1
[patent_app_number] => 09/182904
[patent_app_country] => US
[patent_app_date] => 1998-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3821
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/378/06378012.pdf
[firstpage_image] =>[orig_patent_app_number] => 09182904
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/182904 | Interface with data transmission mode from weighing scale to one or more peripheral devices and mailing machine tripping mode determined by individual peripheral device protocol | Oct 28, 1998 | Issued |
Array
(
[id] => 6908541
[patent_doc_number] => 20010011308
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-02
[patent_title] => 'HANDHELD COMPUTER SYNCHRONIZED WITH A HOST COMPUTER'
[patent_app_type] => new
[patent_app_number] => 09/175866
[patent_app_country] => US
[patent_app_date] => 1998-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 9801
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0011/20010011308.pdf
[firstpage_image] =>[orig_patent_app_number] => 09175866
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/175866 | System for automatic synchronization of common file between portable computer and host computer via communication channel established with user approval of charge to be incurred | Oct 19, 1998 | Issued |
Array
(
[id] => 4317355
[patent_doc_number] => 06185632
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-06
[patent_title] => 'High speed communication protocol for IEEE-1394 including transmission of request and reply writes to a datagram-FIFO-address to exchange commands to end a job'
[patent_app_type] => 1
[patent_app_number] => 9/174820
[patent_app_country] => US
[patent_app_date] => 1998-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2261
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/185/06185632.pdf
[firstpage_image] =>[orig_patent_app_number] => 174820
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/174820 | High speed communication protocol for IEEE-1394 including transmission of request and reply writes to a datagram-FIFO-address to exchange commands to end a job | Oct 18, 1998 | Issued |
Array
(
[id] => 1553712
[patent_doc_number] => 06347344
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-12
[patent_title] => 'Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor'
[patent_app_type] => B1
[patent_app_number] => 09/172286
[patent_app_country] => US
[patent_app_date] => 1998-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 40
[patent_no_of_words] => 28471
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/347/06347344.pdf
[firstpage_image] =>[orig_patent_app_number] => 09172286
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/172286 | Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor | Oct 13, 1998 | Issued |
Array
(
[id] => 1484902
[patent_doc_number] => 06453369
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-17
[patent_title] => 'Access protection from unauthorized use of memory medium using identifier unique to data storage device'
[patent_app_type] => B1
[patent_app_number] => 09/170537
[patent_app_country] => US
[patent_app_date] => 1998-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 30
[patent_no_of_words] => 9566
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/453/06453369.pdf
[firstpage_image] =>[orig_patent_app_number] => 09170537
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/170537 | Access protection from unauthorized use of memory medium using identifier unique to data storage device | Oct 12, 1998 | Issued |
Array
(
[id] => 4254765
[patent_doc_number] => 06119187
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-12
[patent_title] => 'Telecommunication system with universal API using generic messages having user functionality associated with predetermined functions, primitives and logical states for defining PPL component state machines'
[patent_app_type] => 1
[patent_app_number] => 9/168130
[patent_app_country] => US
[patent_app_date] => 1998-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 12690
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 254
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/119/06119187.pdf
[firstpage_image] =>[orig_patent_app_number] => 168130
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/168130 | Telecommunication system with universal API using generic messages having user functionality associated with predetermined functions, primitives and logical states for defining PPL component state machines | Oct 6, 1998 | Issued |
Array
(
[id] => 4290078
[patent_doc_number] => 06308231
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-23
[patent_title] => 'Industrial control systems having input/output circuits with programmable input/output characteristics'
[patent_app_type] => 1
[patent_app_number] => 9/163931
[patent_app_country] => US
[patent_app_date] => 1998-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 7745
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 353
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/308/06308231.pdf
[firstpage_image] =>[orig_patent_app_number] => 163931
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/163931 | Industrial control systems having input/output circuits with programmable input/output characteristics | Sep 28, 1998 | Issued |
Array
(
[id] => 4177217
[patent_doc_number] => 06108720
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-22
[patent_title] => 'Echo canceling modem which dynamically switches sizes of sample buffer between first size for quick response time and second size for robustness to interrupt latency'
[patent_app_type] => 1
[patent_app_number] => 9/163054
[patent_app_country] => US
[patent_app_date] => 1998-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 4584
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/108/06108720.pdf
[firstpage_image] =>[orig_patent_app_number] => 163054
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/163054 | Echo canceling modem which dynamically switches sizes of sample buffer between first size for quick response time and second size for robustness to interrupt latency | Sep 28, 1998 | Issued |
Array
(
[id] => 4373639
[patent_doc_number] => 06292845
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-18
[patent_title] => 'Processing unit having independent execution units for parallel execution of instructions of different category with instructions having specific bits indicating instruction size and category respectively'
[patent_app_type] => 1
[patent_app_number] => 9/140474
[patent_app_country] => US
[patent_app_date] => 1998-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 3383
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/292/06292845.pdf
[firstpage_image] =>[orig_patent_app_number] => 140474
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/140474 | Processing unit having independent execution units for parallel execution of instructions of different category with instructions having specific bits indicating instruction size and category respectively | Aug 25, 1998 | Issued |
Array
(
[id] => 4281392
[patent_doc_number] => 06260152
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-10
[patent_title] => 'Method and apparatus for synchronizing data transfers in a logic circuit having plural clock domains'
[patent_app_type] => 1
[patent_app_number] => 9/126430
[patent_app_country] => US
[patent_app_date] => 1998-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2941
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/260/06260152.pdf
[firstpage_image] =>[orig_patent_app_number] => 126430
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/126430 | Method and apparatus for synchronizing data transfers in a logic circuit having plural clock domains | Jul 29, 1998 | Issued |
Array
(
[id] => 4279381
[patent_doc_number] => 06205493
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-20
[patent_title] => 'State machine for selectively performing an operation on a single or a plurality of registers depending upon the register address specified in a packet'
[patent_app_type] => 1
[patent_app_number] => 9/118337
[patent_app_country] => US
[patent_app_date] => 1998-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 5179
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 220
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/205/06205493.pdf
[firstpage_image] =>[orig_patent_app_number] => 118337
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/118337 | State machine for selectively performing an operation on a single or a plurality of registers depending upon the register address specified in a packet | Jul 15, 1998 | Issued |
Array
(
[id] => 1490051
[patent_doc_number] => 06366968
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-02
[patent_title] => 'Physical write packets processing when posted write error queue is full, with posted write error queue storing physical write requests when posted write packet fails'
[patent_app_type] => B1
[patent_app_number] => 09/105500
[patent_app_country] => US
[patent_app_date] => 1998-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3444
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/366/06366968.pdf
[firstpage_image] =>[orig_patent_app_number] => 09105500
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/105500 | Physical write packets processing when posted write error queue is full, with posted write error queue storing physical write requests when posted write packet fails | Jun 25, 1998 | Issued |
Array
(
[id] => 4317284
[patent_doc_number] => 06328766
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-11
[patent_title] => 'Media element library with non-overlapping subset of media elements and non-overlapping subset of media element drives accessible to first host and unaccessible to second host'
[patent_app_type] => 1
[patent_app_number] => 9/104406
[patent_app_country] => US
[patent_app_date] => 1998-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 5783
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/328/06328766.pdf
[firstpage_image] =>[orig_patent_app_number] => 104406
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/104406 | Media element library with non-overlapping subset of media elements and non-overlapping subset of media element drives accessible to first host and unaccessible to second host | Jun 24, 1998 | Issued |
Array
(
[id] => 4194459
[patent_doc_number] => 06085258
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-04
[patent_title] => 'State machine for selectively performing an operation on a single or a plurality of registers depending upon the register address specified in a packet'
[patent_app_type] => 1
[patent_app_number] => 9/100270
[patent_app_country] => US
[patent_app_date] => 1998-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 5179
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/085/06085258.pdf
[firstpage_image] =>[orig_patent_app_number] => 100270
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/100270 | State machine for selectively performing an operation on a single or a plurality of registers depending upon the register address specified in a packet | Jun 18, 1998 | Issued |