Search

Tanya Theresa Ngo Motsinger

Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )

Most Active Art Unit
2637
Art Unit(s)
2635, 2613, 2637
Total Applications
469
Issued Applications
358
Pending Applications
25
Abandoned Applications
99

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8555052 [patent_doc_number] => 08329524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-11 [patent_title] => 'Surface emitting laser, method for producing surface emitting laser, and image forming apparatus' [patent_app_type] => utility [patent_app_number] => 13/413973 [patent_app_country] => US [patent_app_date] => 2012-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 34 [patent_no_of_words] => 12139 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13413973 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/413973
Surface emitting laser, method for producing surface emitting laser, and image forming apparatus Mar 6, 2012 Issued
Array ( [id] => 9195214 [patent_doc_number] => 20130334529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/002548 [patent_app_country] => US [patent_app_date] => 2012-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 7372 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14002548 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/002548
Semiconductor device with electro-static discharge protection device above semiconductor device area Mar 5, 2012 Issued
Array ( [id] => 8252507 [patent_doc_number] => 20120156830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'METHOD OF FORMING A RING-SHAPED METAL STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/406062 [patent_app_country] => US [patent_app_date] => 2012-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6913 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20120156830.pdf [firstpage_image] =>[orig_patent_app_number] => 13406062 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/406062
Method of forming a ring-shaped metal structure Feb 26, 2012 Issued
Array ( [id] => 8664898 [patent_doc_number] => 08378360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Light emitting package' [patent_app_type] => utility [patent_app_number] => 13/399709 [patent_app_country] => US [patent_app_date] => 2012-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4623 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13399709 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/399709
Light emitting package Feb 16, 2012 Issued
Array ( [id] => 8825983 [patent_doc_number] => 20130127028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'THREE-DIMENSIONAL INTEGRATED CIRCUIT HAVING REDUNDANT RELIEF STRUCTURE FOR CHIP BONDING SECTION' [patent_app_type] => utility [patent_app_number] => 13/812011 [patent_app_country] => US [patent_app_date] => 2012-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12822 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13812011 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/812011
Three-dimensional integrated circuit having redundant relief structure for chip bonding section Jan 10, 2012 Issued
Array ( [id] => 8888545 [patent_doc_number] => 20130161729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'Methods of Forming Isolation Structures on FinFET Semiconductor Devices' [patent_app_type] => utility [patent_app_number] => 13/332676 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5829 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13332676 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/332676
Methods of forming isolation structures on FinFET semiconductor devices Dec 20, 2011 Issued
Array ( [id] => 9127037 [patent_doc_number] => 08574986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-05 [patent_title] => 'Method for fabricating nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 13/331983 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3298 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13331983 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/331983
Method for fabricating nonvolatile memory device Dec 19, 2011 Issued
Array ( [id] => 9250367 [patent_doc_number] => 08614145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-24 [patent_title] => 'Through substrate via formation processing using sacrificial material' [patent_app_type] => utility [patent_app_number] => 13/325191 [patent_app_country] => US [patent_app_date] => 2011-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5519 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13325191 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/325191
Through substrate via formation processing using sacrificial material Dec 13, 2011 Issued
Array ( [id] => 8265385 [patent_doc_number] => 20120164815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'METHOD OF FORMING ELEMENT ISOLATION LAYER' [patent_app_type] => utility [patent_app_number] => 13/324087 [patent_app_country] => US [patent_app_date] => 2011-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5008 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13324087 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/324087
METHOD OF FORMING ELEMENT ISOLATION LAYER Dec 12, 2011 Abandoned
Array ( [id] => 8772336 [patent_doc_number] => 08426291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-23 [patent_title] => 'Method for isolation formation in manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/307759 [patent_app_country] => US [patent_app_date] => 2011-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 44 [patent_no_of_words] => 5197 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13307759 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/307759
Method for isolation formation in manufacturing semiconductor device Nov 29, 2011 Issued
Array ( [id] => 9046730 [patent_doc_number] => 08541284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-24 [patent_title] => 'Method of manufacturing string floating gates with air gaps in between' [patent_app_type] => utility [patent_app_number] => 13/302080 [patent_app_country] => US [patent_app_date] => 2011-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7176 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13302080 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/302080
Method of manufacturing string floating gates with air gaps in between Nov 21, 2011 Issued
Array ( [id] => 9530085 [patent_doc_number] => 08753955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-17 [patent_title] => 'Methods of fabricating nonvolatile memory devices including voids between active regions and related devices' [patent_app_type] => utility [patent_app_number] => 13/300787 [patent_app_country] => US [patent_app_date] => 2011-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 7767 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13300787 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/300787
Methods of fabricating nonvolatile memory devices including voids between active regions and related devices Nov 20, 2011 Issued
Array ( [id] => 8210241 [patent_doc_number] => 20120129316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'METHOD FOR FORMING FINE PATTERN OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/301351 [patent_app_country] => US [patent_app_date] => 2011-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3111 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20120129316.pdf [firstpage_image] =>[orig_patent_app_number] => 13301351 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/301351
Method for forming fine pattern of semiconductor device Nov 20, 2011 Issued
Array ( [id] => 8968545 [patent_doc_number] => 08507356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-13 [patent_title] => 'Formation of wells utilizing masks in manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/297414 [patent_app_country] => US [patent_app_date] => 2011-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 10002 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13297414 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/297414
Formation of wells utilizing masks in manufacturing semiconductor device Nov 15, 2011 Issued
Array ( [id] => 8821640 [patent_doc_number] => 20130122686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'Reverse Tone STI Formation' [patent_app_type] => utility [patent_app_number] => 13/298112 [patent_app_country] => US [patent_app_date] => 2011-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13298112 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/298112
Methods for epitaxially growing active regions between STI regions Nov 15, 2011 Issued
Array ( [id] => 8747438 [patent_doc_number] => RE044140 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2013-04-09 [patent_title] => 'Bipolar method and structure having improved BVCEO/RCS trade-off made with depletable collector columns' [patent_app_type] => reissue [patent_app_number] => 13/295764 [patent_app_country] => US [patent_app_date] => 2011-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 34 [patent_no_of_words] => 8196 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13295764 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/295764
Bipolar method and structure having improved BVCEO/RCS trade-off made with depletable collector columns Nov 13, 2011 Issued
Array ( [id] => 8224823 [patent_doc_number] => 20120139034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'Process For Manufacturing A MOS Device With Intercell Ion Implant' [patent_app_type] => utility [patent_app_number] => 13/292003 [patent_app_country] => US [patent_app_date] => 2011-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4000 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13292003 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/292003
Process for manufacturing a MOS device with intercell ion implant confined to the gate electrode region Nov 7, 2011 Issued
Array ( [id] => 8933158 [patent_doc_number] => 08492860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Magnetic random access memory with switching assist layer' [patent_app_type] => utility [patent_app_number] => 13/289372 [patent_app_country] => US [patent_app_date] => 2011-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 7711 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13289372 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/289372
Magnetic random access memory with switching assist layer Nov 3, 2011 Issued
Array ( [id] => 11265893 [patent_doc_number] => 09490196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-08 [patent_title] => 'Multi die package having a die and a spacer layer in a recess' [patent_app_type] => utility [patent_app_number] => 13/977183 [patent_app_country] => US [patent_app_date] => 2011-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6228 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13977183 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/977183
Multi die package having a die and a spacer layer in a recess Oct 30, 2011 Issued
Array ( [id] => 9413462 [patent_doc_number] => 08697498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-15 [patent_title] => 'Methods of manufacturing three dimensional semiconductor memory devices using sub-plates' [patent_app_type] => utility [patent_app_number] => 13/284435 [patent_app_country] => US [patent_app_date] => 2011-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 7644 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13284435 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/284435
Methods of manufacturing three dimensional semiconductor memory devices using sub-plates Oct 27, 2011 Issued
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