| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 6157021
[patent_doc_number] => 20110157754
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-30
[patent_title] => 'Electrostatic discharge protection method and device for semiconductor device including an electrostatic discharge protection element providing a discharge path of a surge current'
[patent_app_type] => utility
[patent_app_number] => 13/064087
[patent_app_country] => US
[patent_app_date] => 2011-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 8266
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0157/20110157754.pdf
[firstpage_image] =>[orig_patent_app_number] => 13064087
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/064087 | Electrostatic discharge protection method and device for semiconductor device including an electrostatic discharge protection element providing a discharge path of a surge current | Mar 3, 2011 | Issued |
Array
(
[id] => 8091325
[patent_doc_number] => 20120081273
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-05
[patent_title] => 'PIXEL STRUCTURE, PIXEL ARRAY AND DISPLAY PANEL'
[patent_app_type] => utility
[patent_app_number] => 13/040273
[patent_app_country] => US
[patent_app_date] => 2011-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4175
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0081/20120081273.pdf
[firstpage_image] =>[orig_patent_app_number] => 13040273
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/040273 | PIXEL STRUCTURE, PIXEL ARRAY AND DISPLAY PANEL | Mar 3, 2011 | Abandoned |
Array
(
[id] => 4624698
[patent_doc_number] => 08003997
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-08-23
[patent_title] => 'Package for light emitting device'
[patent_app_type] => utility
[patent_app_number] => 13/036947
[patent_app_country] => US
[patent_app_date] => 2011-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 4547
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/003/08003997.pdf
[firstpage_image] =>[orig_patent_app_number] => 13036947
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/036947 | Package for light emitting device | Feb 27, 2011 | Issued |
Array
(
[id] => 8125279
[patent_doc_number] => 20120087185
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-12
[patent_title] => 'MAGNETIC LATCH MAGNETIC RANDOM ACCESS MEMORY (MRAM)'
[patent_app_type] => utility
[patent_app_number] => 13/035857
[patent_app_country] => US
[patent_app_date] => 2011-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6026
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0087/20120087185.pdf
[firstpage_image] =>[orig_patent_app_number] => 13035857
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/035857 | Spin-transfer torque magnetic random access memory with multi-layered storage layer | Feb 24, 2011 | Issued |
Array
(
[id] => 8955743
[patent_doc_number] => 08501515
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-08-06
[patent_title] => 'Methods of forming micro-electromechanical resonators using passive compensation techniques'
[patent_app_type] => utility
[patent_app_number] => 13/035148
[patent_app_country] => US
[patent_app_date] => 2011-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 22
[patent_no_of_words] => 4521
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 254
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13035148
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/035148 | Methods of forming micro-electromechanical resonators using passive compensation techniques | Feb 24, 2011 | Issued |
Array
(
[id] => 8359133
[patent_doc_number] => 20120214285
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-23
[patent_title] => 'Methods Of Forming A Vertical Transistor And At Least A Conductive Line Electrically Coupled Therewith, Methods Of Forming Memory Cells, And Methods Of Forming Arrays Of Memory Cells'
[patent_app_type] => utility
[patent_app_number] => 13/031829
[patent_app_country] => US
[patent_app_date] => 2011-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 4295
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13031829
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/031829 | Methods of forming a vertical transistor and at least a conductive line electrically coupled therewith | Feb 21, 2011 | Issued |
Array
(
[id] => 7988917
[patent_doc_number] => 08076756
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-12-13
[patent_title] => 'Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures'
[patent_app_type] => utility
[patent_app_number] => 13/031195
[patent_app_country] => US
[patent_app_date] => 2011-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 24
[patent_no_of_words] => 9914
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/076/08076756.pdf
[firstpage_image] =>[orig_patent_app_number] => 13031195
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/031195 | Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures | Feb 18, 2011 | Issued |
Array
(
[id] => 8807691
[patent_doc_number] => 08445343
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-05-21
[patent_title] => 'Methods of fabricating semiconductor devices including semiconductor layers formed in stacked insulating layers'
[patent_app_type] => utility
[patent_app_number] => 13/030729
[patent_app_country] => US
[patent_app_date] => 2011-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 9071
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13030729
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/030729 | Methods of fabricating semiconductor devices including semiconductor layers formed in stacked insulating layers | Feb 17, 2011 | Issued |
Array
(
[id] => 7763495
[patent_doc_number] => 08115243
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-02-14
[patent_title] => 'Surround gate access transistors with grown ultra-thin bodies'
[patent_app_type] => utility
[patent_app_number] => 13/027154
[patent_app_country] => US
[patent_app_date] => 2011-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 19
[patent_no_of_words] => 4765
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/115/08115243.pdf
[firstpage_image] =>[orig_patent_app_number] => 13027154
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/027154 | Surround gate access transistors with grown ultra-thin bodies | Feb 13, 2011 | Issued |
Array
(
[id] => 6057776
[patent_doc_number] => 20110198027
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-08-18
[patent_title] => 'METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 13/025879
[patent_app_country] => US
[patent_app_date] => 2011-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6159
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0198/20110198027.pdf
[firstpage_image] =>[orig_patent_app_number] => 13025879
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/025879 | METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE | Feb 10, 2011 | Abandoned |
Array
(
[id] => 8933151
[patent_doc_number] => 08492853
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-07-23
[patent_title] => 'Field effect transistor having conductor electrode in contact with semiconductor layer'
[patent_app_type] => utility
[patent_app_number] => 13/014061
[patent_app_country] => US
[patent_app_date] => 2011-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 31
[patent_no_of_words] => 11185
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13014061
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/014061 | Field effect transistor having conductor electrode in contact with semiconductor layer | Jan 25, 2011 | Issued |
Array
(
[id] => 8797531
[patent_doc_number] => 08436403
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-05-07
[patent_title] => 'Semiconductor device including transistor provided with sidewall and electronic appliance'
[patent_app_type] => utility
[patent_app_number] => 13/014081
[patent_app_country] => US
[patent_app_date] => 2011-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 24
[patent_no_of_words] => 16135
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13014081
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/014081 | Semiconductor device including transistor provided with sidewall and electronic appliance | Jan 25, 2011 | Issued |
Array
(
[id] => 6042332
[patent_doc_number] => 20110204409
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-08-25
[patent_title] => 'hBN INSULATOR LAYERS AND ASSOCIATED METHODS'
[patent_app_type] => utility
[patent_app_number] => 13/014105
[patent_app_country] => US
[patent_app_date] => 2011-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 7089
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0204/20110204409.pdf
[firstpage_image] =>[orig_patent_app_number] => 13014105
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/014105 | hBN INSULATOR LAYERS AND ASSOCIATED METHODS | Jan 25, 2011 | Abandoned |
Array
(
[id] => 8797559
[patent_doc_number] => 08436431
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-05-07
[patent_title] => 'Semiconductor device including gate and three conductor electrodes'
[patent_app_type] => utility
[patent_app_number] => 13/014060
[patent_app_country] => US
[patent_app_date] => 2011-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 18
[patent_no_of_words] => 8490
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13014060
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/014060 | Semiconductor device including gate and three conductor electrodes | Jan 25, 2011 | Issued |
Array
(
[id] => 6106120
[patent_doc_number] => 20110186952
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-08-04
[patent_title] => 'SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING THEREOF, AND ELECTRONIC APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 13/013981
[patent_app_country] => US
[patent_app_date] => 2011-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 11516
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0186/20110186952.pdf
[firstpage_image] =>[orig_patent_app_number] => 13013981
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/013981 | Solid-state imaging device, method of manufacturing thereof, and electronic apparatus | Jan 25, 2011 | Issued |
Array
(
[id] => 7738877
[patent_doc_number] => 20120018847
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-01-26
[patent_title] => 'GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/013825
[patent_app_country] => US
[patent_app_date] => 2011-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1148
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0018/20120018847.pdf
[firstpage_image] =>[orig_patent_app_number] => 13013825
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/013825 | Gallium nitride-based semiconductor device and method for manufacturing the same | Jan 25, 2011 | Issued |
Array
(
[id] => 8310522
[patent_doc_number] => 20120187538
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-07-26
[patent_title] => 'BIPOLAR TRANSISTOR WITH IMPROVED GAIN'
[patent_app_type] => utility
[patent_app_number] => 13/014029
[patent_app_country] => US
[patent_app_date] => 2011-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 10212
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13014029
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/014029 | Bipolar transistor with two different emitter portions having same type dopant of different concentrations for improved gain | Jan 25, 2011 | Issued |
Array
(
[id] => 6058691
[patent_doc_number] => 20110198558
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-08-18
[patent_title] => 'GRAPHENE CIRCUIT BOARD HAVING IMPROVED ELECTRICAL CONTACT BETWEEN GRAPHENE AND METAL ELECTRODE, AND DEVICE INCLUDING SAME'
[patent_app_type] => utility
[patent_app_number] => 13/013984
[patent_app_country] => US
[patent_app_date] => 2011-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7132
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0198/20110198558.pdf
[firstpage_image] =>[orig_patent_app_number] => 13013984
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/013984 | Circuit board including a graphene film having contact region covering a recessed region and a patterned metal film covering the contact region and in direct electrical contact therewith, and device including same | Jan 25, 2011 | Issued |
Array
(
[id] => 8835068
[patent_doc_number] => 08450827
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-05-28
[patent_title] => 'MOS varactor structure and methods'
[patent_app_type] => utility
[patent_app_number] => 13/013677
[patent_app_country] => US
[patent_app_date] => 2011-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 5786
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 272
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13013677
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/013677 | MOS varactor structure and methods | Jan 24, 2011 | Issued |
Array
(
[id] => 8652959
[patent_doc_number] => 08372705
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-02-12
[patent_title] => 'Fabrication of CMOS transistors having differentially stressed spacers'
[patent_app_type] => utility
[patent_app_number] => 13/013801
[patent_app_country] => US
[patent_app_date] => 2011-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2767
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 291
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13013801
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/013801 | Fabrication of CMOS transistors having differentially stressed spacers | Jan 24, 2011 | Issued |