Search

Tanya Theresa Ngo Motsinger

Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )

Most Active Art Unit
2637
Art Unit(s)
2635, 2613, 2637
Total Applications
469
Issued Applications
358
Pending Applications
25
Abandoned Applications
99

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6053328 [patent_doc_number] => 20110109688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'SILICON/GERMANIUM OXIDE PARTICLE INKS, INKJET PRINTING AND PROCESSES FOR DOPING SEMICONDUCTOR SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 13/011596 [patent_app_country] => US [patent_app_date] => 2011-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 12692 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20110109688.pdf [firstpage_image] =>[orig_patent_app_number] => 13011596 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/011596
Silicon/germanium oxide particle inks, inkjet printing and processes for doping semiconductor substrates Jan 20, 2011 Issued
Array ( [id] => 8002375 [patent_doc_number] => RE043042 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2011-12-27 [patent_title] => 'Bipolar method and structure having improved BVCEO/RCS trade-off made with depletable collector columns' [patent_app_type] => reissue [patent_app_number] => 12/985856 [patent_app_country] => US [patent_app_date] => 2011-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 44 [patent_no_of_words] => 8070 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/043/RE043042.pdf [firstpage_image] =>[orig_patent_app_number] => 12985856 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/985856
Bipolar method and structure having improved BVCEO/RCS trade-off made with depletable collector columns Jan 5, 2011 Issued
Array ( [id] => 6102257 [patent_doc_number] => 20110165750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-07 [patent_title] => 'METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING STRUCTURES' [patent_app_type] => utility [patent_app_number] => 12/984940 [patent_app_country] => US [patent_app_date] => 2011-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6577 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20110165750.pdf [firstpage_image] =>[orig_patent_app_number] => 12984940 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/984940
METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING STRUCTURES Jan 4, 2011 Abandoned
Array ( [id] => 9589901 [patent_doc_number] => 08779441 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Semiconductor light emitting element with first and second electrode openings arranged at a constant distance' [patent_app_type] => utility [patent_app_number] => 13/513492 [patent_app_country] => US [patent_app_date] => 2010-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 13069 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13513492 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/513492
Semiconductor light emitting element with first and second electrode openings arranged at a constant distance Dec 1, 2010 Issued
Array ( [id] => 4624776 [patent_doc_number] => 08004077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Interconnection of land section to wiring layers at center of external connection terminals in semiconductor device and manufacturing thereof' [patent_app_type] => utility [patent_app_number] => 12/947861 [patent_app_country] => US [patent_app_date] => 2010-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 7865 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/004/08004077.pdf [firstpage_image] =>[orig_patent_app_number] => 12947861 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/947861
Interconnection of land section to wiring layers at center of external connection terminals in semiconductor device and manufacturing thereof Nov 16, 2010 Issued
Array ( [id] => 6021202 [patent_doc_number] => 20110049528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'METHODS FOR FABRICATING COMPOUND MATERIAL WAFERS' [patent_app_type] => utility [patent_app_number] => 12/939590 [patent_app_country] => US [patent_app_date] => 2010-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4925 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20110049528.pdf [firstpage_image] =>[orig_patent_app_number] => 12939590 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/939590
Reconditioned substrates for fabricating compound material wafers Nov 3, 2010 Issued
Array ( [id] => 9184357 [patent_doc_number] => 08624294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Semiconductor with power generating photovoltaic layer' [patent_app_type] => utility [patent_app_number] => 12/938173 [patent_app_country] => US [patent_app_date] => 2010-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9965 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12938173 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/938173
Semiconductor with power generating photovoltaic layer Nov 1, 2010 Issued
Array ( [id] => 10557227 [patent_doc_number] => 09281434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Infra red detectors and a method of manufacturing infra red detectors using MOVPE' [patent_app_type] => utility [patent_app_number] => 13/512836 [patent_app_country] => US [patent_app_date] => 2010-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1597 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13512836 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/512836
Infra red detectors and a method of manufacturing infra red detectors using MOVPE Nov 1, 2010 Issued
Array ( [id] => 7569919 [patent_doc_number] => 20110265574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'System on a Chip Using Integrated MEMS and CMOS Devices' [patent_app_type] => utility [patent_app_number] => 12/913440 [patent_app_country] => US [patent_app_date] => 2010-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8412 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20110265574.pdf [firstpage_image] =>[orig_patent_app_number] => 12913440 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/913440
Integrated system on chip using multiple MEMS and CMOS devices Oct 26, 2010 Issued
Array ( [id] => 5948409 [patent_doc_number] => 20110031563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-10 [patent_title] => 'Method for Manufacturing a Semiconductor Device Having Doped and Undoped Polysilicon Layers' [patent_app_type] => utility [patent_app_number] => 12/910239 [patent_app_country] => US [patent_app_date] => 2010-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6275 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20110031563.pdf [firstpage_image] =>[orig_patent_app_number] => 12910239 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/910239
Semiconductor device having a polysilicon layer with a non-constant doping profile Oct 21, 2010 Issued
Array ( [id] => 5993130 [patent_doc_number] => 20110014783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-20 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING ELECTRODE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/888995 [patent_app_country] => US [patent_app_date] => 2010-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 11807 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20110014783.pdf [firstpage_image] =>[orig_patent_app_number] => 12888995 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/888995
Semiconductor device having electrode and manufacturing method thereof Sep 22, 2010 Issued
Array ( [id] => 6134817 [patent_doc_number] => 20110008719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-13 [patent_title] => 'METHOD AND APPARATUS FOR MEASUREMENT AND CONTROL OF PHOTOMASK TO SUBSTRATE ALIGNMENT' [patent_app_type] => utility [patent_app_number] => 12/888600 [patent_app_country] => US [patent_app_date] => 2010-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6528 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20110008719.pdf [firstpage_image] =>[orig_patent_app_number] => 12888600 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/888600
Method and apparatus for measurement and control of photomask to substrate alignment Sep 22, 2010 Issued
Array ( [id] => 5991534 [patent_doc_number] => 20110013187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-20 [patent_title] => 'METHOD AND APPARATUS FOR MEASUREMENT AND CONTROL OF PHOTOMASK TO SUBSTRATE ALIGNMENT' [patent_app_type] => utility [patent_app_number] => 12/888697 [patent_app_country] => US [patent_app_date] => 2010-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6528 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20110013187.pdf [firstpage_image] =>[orig_patent_app_number] => 12888697 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/888697
Method and apparatus for measurement and control of photomask to substrate alignment Sep 22, 2010 Issued
Array ( [id] => 5974330 [patent_doc_number] => 20110069455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-24 [patent_title] => 'Power Semiconductor Module for Inverter Circuit System' [patent_app_type] => utility [patent_app_number] => 12/886904 [patent_app_country] => US [patent_app_date] => 2010-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 25434 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20110069455.pdf [firstpage_image] =>[orig_patent_app_number] => 12886904 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/886904
Power semiconductor module for inverter circuit system Sep 20, 2010 Issued
Array ( [id] => 7490474 [patent_doc_number] => 08030181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-04 [patent_title] => 'Electrical fuse circuit for security applications' [patent_app_type] => utility [patent_app_number] => 12/881944 [patent_app_country] => US [patent_app_date] => 2010-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3803 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/030/08030181.pdf [firstpage_image] =>[orig_patent_app_number] => 12881944 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/881944
Electrical fuse circuit for security applications Sep 13, 2010 Issued
Array ( [id] => 4499261 [patent_doc_number] => 07948030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'Semiconductor constructions of memory devices with different sizes of GateLine trenches' [patent_app_type] => utility [patent_app_number] => 12/875828 [patent_app_country] => US [patent_app_date] => 2010-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 6059 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/948/07948030.pdf [firstpage_image] =>[orig_patent_app_number] => 12875828 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/875828
Semiconductor constructions of memory devices with different sizes of GateLine trenches Sep 2, 2010 Issued
Array ( [id] => 6569934 [patent_doc_number] => 20100320473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'THIN FILM TRANSISTOR STRUCTURE OF PIXEL' [patent_app_type] => utility [patent_app_number] => 12/869754 [patent_app_country] => US [patent_app_date] => 2010-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2601 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0320/20100320473.pdf [firstpage_image] =>[orig_patent_app_number] => 12869754 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/869754
Thin film transistor structure of pixel with drain extensions overlapping gate electrode and gate electrode extention Aug 26, 2010 Issued
Array ( [id] => 8202715 [patent_doc_number] => 08188479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-29 [patent_title] => 'Pixel electrode structure having via holes disposed on common line with high display quality' [patent_app_type] => utility [patent_app_number] => 12/868752 [patent_app_country] => US [patent_app_date] => 2010-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5170 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/188/08188479.pdf [firstpage_image] =>[orig_patent_app_number] => 12868752 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/868752
Pixel electrode structure having via holes disposed on common line with high display quality Aug 25, 2010 Issued
Array ( [id] => 4644346 [patent_doc_number] => 08021951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-20 [patent_title] => 'Formation of longitudinal bipolar transistor with base region in trenches having emitter and collector regions disposed along portions of side surfaces of base region' [patent_app_type] => utility [patent_app_number] => 12/807000 [patent_app_country] => US [patent_app_date] => 2010-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 6571 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/021/08021951.pdf [firstpage_image] =>[orig_patent_app_number] => 12807000 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/807000
Formation of longitudinal bipolar transistor with base region in trenches having emitter and collector regions disposed along portions of side surfaces of base region Aug 24, 2010 Issued
Array ( [id] => 8690570 [patent_doc_number] => 08390099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Interconnection substrate having first and second insulating films with an adhesion enhancing layer therebetween' [patent_app_type] => utility [patent_app_number] => 12/862140 [patent_app_country] => US [patent_app_date] => 2010-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 8610 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12862140 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/862140
Interconnection substrate having first and second insulating films with an adhesion enhancing layer therebetween Aug 23, 2010 Issued
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