Search

Tanya Theresa Ngo Motsinger

Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )

Most Active Art Unit
2637
Art Unit(s)
2635, 2613, 2637
Total Applications
469
Issued Applications
358
Pending Applications
25
Abandoned Applications
99

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7815038 [patent_doc_number] => 20120061658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'STRUCTURAL TEMPLATING FOR ORGANIC ELECTRONIC DEVICES HAVING AN ORGANIC FILM WITH LONG RANGE ORDER' [patent_app_type] => utility [patent_app_number] => 13/319932 [patent_app_country] => US [patent_app_date] => 2010-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11118 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20120061658.pdf [firstpage_image] =>[orig_patent_app_number] => 13319932 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/319932
STRUCTURAL TEMPLATING FOR ORGANIC ELECTRONIC DEVICES HAVING AN ORGANIC FILM WITH LONG RANGE ORDER Jun 2, 2010 Abandoned
Array ( [id] => 7651427 [patent_doc_number] => 20110300696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-08 [patent_title] => 'METHOD FOR DAMAGE-FREE JUNCTION FORMATION' [patent_app_type] => utility [patent_app_number] => 12/792190 [patent_app_country] => US [patent_app_date] => 2010-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3325 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20110300696.pdf [firstpage_image] =>[orig_patent_app_number] => 12792190 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/792190
METHOD FOR DAMAGE-FREE JUNCTION FORMATION Jun 1, 2010 Abandoned
Array ( [id] => 8533282 [patent_doc_number] => 08309436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-13 [patent_title] => 'Method of producing epitaxial substrate with gettering for solid-state imaging device, and method of producing solid-state imaging device using same substrate' [patent_app_type] => utility [patent_app_number] => 12/789649 [patent_app_country] => US [patent_app_date] => 2010-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5699 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12789649 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/789649
Method of producing epitaxial substrate with gettering for solid-state imaging device, and method of producing solid-state imaging device using same substrate May 27, 2010 Issued
Array ( [id] => 9255205 [patent_doc_number] => 08618624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-31 [patent_title] => 'UV curable encapsulant' [patent_app_type] => utility [patent_app_number] => 13/696174 [patent_app_country] => US [patent_app_date] => 2010-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3481 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13696174 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/696174
UV curable encapsulant May 2, 2010 Issued
Array ( [id] => 6532161 [patent_doc_number] => 20100270512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'ELECTRICALLY CONNECTED GRAPHENE-METAL ELECTRODE DEVICE, AND ELECTRONIC DEVICE, ELECTRONIC INTEGRATED CIRCUIT AND ELECTRO-OPTICAL INTEGRATED CIRCUIT USING SAME' [patent_app_type] => utility [patent_app_number] => 12/766960 [patent_app_country] => US [patent_app_date] => 2010-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2878 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20100270512.pdf [firstpage_image] =>[orig_patent_app_number] => 12766960 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/766960
Electrically connected graphene-metal electrode device, and electronic device, electronic integrated circuit and electro-optical integrated circuit using same Apr 25, 2010 Issued
Array ( [id] => 6461130 [patent_doc_number] => 20100190304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'SEMICONDUCTOR STORAGE DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/752832 [patent_app_country] => US [patent_app_date] => 2010-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3245 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20100190304.pdf [firstpage_image] =>[orig_patent_app_number] => 12752832 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/752832
SEMICONDUCTOR STORAGE DEVICE AND METHOD OF FABRICATING THE SAME Mar 31, 2010 Abandoned
Array ( [id] => 6289389 [patent_doc_number] => 20100238636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'STRETCHABLE CIRCUIT CONFIGURATION' [patent_app_type] => utility [patent_app_number] => 12/728814 [patent_app_country] => US [patent_app_date] => 2010-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20100238636.pdf [firstpage_image] =>[orig_patent_app_number] => 12728814 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/728814
Stretchable circuit configuration Mar 21, 2010 Issued
Array ( [id] => 7742802 [patent_doc_number] => 20120021233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-26 [patent_title] => 'METHOD FO PRODUCING SEMICONDUCTOR CHIP STACK, AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/255799 [patent_app_country] => US [patent_app_date] => 2010-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 13961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20120021233.pdf [firstpage_image] =>[orig_patent_app_number] => 13255799 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/255799
Method of producing semiconductor chip laminate comprising an adhesive that comprises a curing compound, curing agent and spacer particles Mar 9, 2010 Issued
Array ( [id] => 7742802 [patent_doc_number] => 20120021233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-26 [patent_title] => 'METHOD FO PRODUCING SEMICONDUCTOR CHIP STACK, AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/255799 [patent_app_country] => US [patent_app_date] => 2010-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 13961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20120021233.pdf [firstpage_image] =>[orig_patent_app_number] => 13255799 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/255799
Method of producing semiconductor chip laminate comprising an adhesive that comprises a curing compound, curing agent and spacer particles Mar 9, 2010 Issued
Array ( [id] => 4093 [patent_doc_number] => 07816207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Semiconductor device having electrode and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/719524 [patent_app_country] => US [patent_app_date] => 2010-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 43 [patent_no_of_words] => 11865 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/816/07816207.pdf [firstpage_image] =>[orig_patent_app_number] => 12719524 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/719524
Semiconductor device having electrode and manufacturing method thereof Mar 7, 2010 Issued
Array ( [id] => 6282050 [patent_doc_number] => 20100156388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'CASCODE CURRENT MIRROR AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/715941 [patent_app_country] => US [patent_app_date] => 2010-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8409 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20100156388.pdf [firstpage_image] =>[orig_patent_app_number] => 12715941 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/715941
Cascode current mirror and method Mar 1, 2010 Issued
Array ( [id] => 6403499 [patent_doc_number] => 20100139852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'METHOD FOR HIGH-VOLUME PRODUCTION OF LIGHT EMITTING DIODES WITH ATTACHED LENSES' [patent_app_type] => utility [patent_app_number] => 12/703640 [patent_app_country] => US [patent_app_date] => 2010-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3735 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20100139852.pdf [firstpage_image] =>[orig_patent_app_number] => 12703640 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/703640
METHOD FOR HIGH-VOLUME PRODUCTION OF LIGHT EMITTING DIODES WITH ATTACHED LENSES Feb 9, 2010 Abandoned
Array ( [id] => 4523011 [patent_doc_number] => 07951645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Power module for low thermal resistance and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 12/702615 [patent_app_country] => US [patent_app_date] => 2010-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3483 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/951/07951645.pdf [firstpage_image] =>[orig_patent_app_number] => 12702615 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/702615
Power module for low thermal resistance and method of fabricating the same Feb 8, 2010 Issued
Array ( [id] => 7772976 [patent_doc_number] => 20120037907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'Method of Forming Source and Drain Electrodes of Organic Thin Film Transistors by Electroless Plating' [patent_app_type] => utility [patent_app_number] => 13/144110 [patent_app_country] => US [patent_app_date] => 2010-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6165 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20120037907.pdf [firstpage_image] =>[orig_patent_app_number] => 13144110 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/144110
Method of Forming Source and Drain Electrodes of Organic Thin Film Transistors by Electroless Plating Jan 26, 2010 Abandoned
Array ( [id] => 7755872 [patent_doc_number] => 20120028438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-02 [patent_title] => 'METHOD FOR SEPARATING A LAYER SYSTEM COMPRISING A WAFER' [patent_app_type] => utility [patent_app_number] => 13/141470 [patent_app_country] => US [patent_app_date] => 2009-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 12940 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20120028438.pdf [firstpage_image] =>[orig_patent_app_number] => 13141470 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/141470
Method for separating a layer system comprising a wafer by precisely maintaining the position of the separating front Dec 22, 2009 Issued
Array ( [id] => 14423 [patent_doc_number] => 07808041 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-05 [patent_title] => 'Semiconductor constructions of memory device with different depth gate line trenches' [patent_app_type] => utility [patent_app_number] => 12/628910 [patent_app_country] => US [patent_app_date] => 2009-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 6015 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/808/07808041.pdf [firstpage_image] =>[orig_patent_app_number] => 12628910 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/628910
Semiconductor constructions of memory device with different depth gate line trenches Nov 30, 2009 Issued
Array ( [id] => 8164299 [patent_doc_number] => 08173506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'Method of forming buried gate electrode utilizing formation of conformal gate oxide and gate electrode layers' [patent_app_type] => utility [patent_app_number] => 12/626959 [patent_app_country] => US [patent_app_date] => 2009-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 4548 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/173/08173506.pdf [firstpage_image] =>[orig_patent_app_number] => 12626959 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/626959
Method of forming buried gate electrode utilizing formation of conformal gate oxide and gate electrode layers Nov 29, 2009 Issued
Array ( [id] => 6295179 [patent_doc_number] => 20100065968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-18 [patent_title] => 'ELECTRONIC APPARATUS INTERCONNECT ROUTING' [patent_app_type] => utility [patent_app_number] => 12/624005 [patent_app_country] => US [patent_app_date] => 2009-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20100065968.pdf [firstpage_image] =>[orig_patent_app_number] => 12624005 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/624005
Electronic apparatus interconnect routing Nov 22, 2009 Issued
Array ( [id] => 7977377 [patent_doc_number] => 08071435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-06 [patent_title] => 'Manufacture of semiconductor device with stress structure' [patent_app_type] => utility [patent_app_number] => 12/606720 [patent_app_country] => US [patent_app_date] => 2009-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 20 [patent_no_of_words] => 6102 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/071/08071435.pdf [firstpage_image] =>[orig_patent_app_number] => 12606720 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/606720
Manufacture of semiconductor device with stress structure Oct 26, 2009 Issued
Array ( [id] => 6473622 [patent_doc_number] => 20100041208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'SEMICONDUCTOR DEVICE MANUFACTURED WITH A DOUBLE SHALLOW TRENCH ISOLATION PROCESS' [patent_app_type] => utility [patent_app_number] => 12/605941 [patent_app_country] => US [patent_app_date] => 2009-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4683 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20100041208.pdf [firstpage_image] =>[orig_patent_app_number] => 12605941 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/605941
Semiconductor device manufactured with a double shallow trench isolation process Oct 25, 2009 Issued
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