
Tanya Theresa Ngo Motsinger
Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )
| Most Active Art Unit | 2637 |
| Art Unit(s) | 2635, 2613, 2637 |
| Total Applications | 469 |
| Issued Applications | 358 |
| Pending Applications | 25 |
| Abandoned Applications | 99 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5085469
[patent_doc_number] => 20070275520
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-29
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/798523
[patent_app_country] => US
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[pdf_file] => publications/A1/0275/20070275520.pdf
[firstpage_image] =>[orig_patent_app_number] => 11798523
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/798523 | Method of manufacturing semiconductor device using alignment mark and mark hole | May 14, 2007 | Issued |
Array
(
[id] => 5259241
[patent_doc_number] => 20070212873
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[patent_kind] => A1
[patent_issue_date] => 2007-09-13
[patent_title] => 'Guard Ring for Improved Matching'
[patent_app_type] => utility
[patent_app_number] => 11/748569
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/748569 | Guard ring for improved matching | May 14, 2007 | Issued |
Array
(
[id] => 4775965
[patent_doc_number] => 20080283963
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-20
[patent_title] => 'Electrical Fuse Circuit for Security Applications'
[patent_app_type] => utility
[patent_app_number] => 11/748959
[patent_app_country] => US
[patent_app_date] => 2007-05-15
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[firstpage_image] =>[orig_patent_app_number] => 11748959
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/748959 | Electrical fuse circuit for security applications | May 14, 2007 | Issued |
Array
(
[id] => 4836882
[patent_doc_number] => 20080277765
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-13
[patent_title] => 'INHIBITING DAMAGE FROM DICING AND CHIP PACKAGING INTERACTION FAILURES IN BACK END OF LINE STRUCTURES'
[patent_app_type] => utility
[patent_app_number] => 11/746684
[patent_app_country] => US
[patent_app_date] => 2007-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
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[firstpage_image] =>[orig_patent_app_number] => 11746684
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/746684 | Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structures | May 9, 2007 | Issued |
Array
(
[id] => 5163139
[patent_doc_number] => 20070284720
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[patent_issue_date] => 2007-12-13
[patent_title] => 'Power semiconductor device and method for its production'
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[firstpage_image] =>[orig_patent_app_number] => 11746699
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/746699 | Power semiconductor device connected in distinct layers of plastic | May 9, 2007 | Issued |
Array
(
[id] => 5532541
[patent_doc_number] => 20090232329
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[patent_kind] => A1
[patent_issue_date] => 2009-09-17
[patent_title] => 'EQUALIZATION METHOD USING EQUAL LOUDNESS CURVE, AND SOUND OUTPUT APPARATUS USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/302389
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[pdf_file] => publications/A1/0232/20090232329.pdf
[firstpage_image] =>[orig_patent_app_number] => 12302389
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/302389 | Equalization method using equal loudness curve based on the IS0266:2003 standard, and sound output apparatus using the same | May 8, 2007 | Issued |
Array
(
[id] => 32446
[patent_doc_number] => 07790529
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[patent_issue_date] => 2010-09-07
[patent_title] => 'Methods of forming memory arrays and semiconductor constructions'
[patent_app_type] => utility
[patent_app_number] => 11/745783
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11745783
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/745783 | Methods of forming memory arrays and semiconductor constructions | May 7, 2007 | Issued |
Array
(
[id] => 817465
[patent_doc_number] => 07411273
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[patent_issue_date] => 2008-08-12
[patent_title] => 'Nitride semiconductor substrate'
[patent_app_type] => utility
[patent_app_number] => 11/744889
[patent_app_country] => US
[patent_app_date] => 2007-05-07
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[patent_drawing_sheets_cnt] => 3
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[firstpage_image] =>[orig_patent_app_number] => 11744889
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/744889 | Nitride semiconductor substrate | May 6, 2007 | Issued |
Array
(
[id] => 33670
[patent_doc_number] => 07791166
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[patent_title] => 'Formation of dummy features and inductors in semiconductor fabrication'
[patent_app_type] => utility
[patent_app_number] => 11/744248
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/744248 | Formation of dummy features and inductors in semiconductor fabrication | May 3, 2007 | Issued |
Array
(
[id] => 132812
[patent_doc_number] => 07701048
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[patent_issue_date] => 2010-04-20
[patent_title] => 'Power module for low thermal resistance and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/743829
[patent_app_country] => US
[patent_app_date] => 2007-05-03
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[firstpage_image] =>[orig_patent_app_number] => 11743829
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/743829 | Power module for low thermal resistance and method of fabricating the same | May 2, 2007 | Issued |
Array
(
[id] => 5066672
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[patent_title] => 'STRUCTURE AND METHOD TO INDUCE STRAIN IN A SEMICONDUCTOR DEVICE CHANNEL WITH STRESSED FILM UNDER THE GATE'
[patent_app_type] => utility
[patent_app_number] => 11/738883
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Array
(
[id] => 377038
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[patent_title] => 'Semiconductor device and method of manufacture thereof'
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Array
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Array
(
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[patent_title] => 'SEMICONDUCTOR DEVICE, LED PRINTHEAD, AND IMAGE FORMING APPARATUS'
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Array
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Array
(
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Array
(
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/295740 | Submount for optical device and its manufacturing method | Apr 3, 2007 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/694907 | Integrated circuit package system with protected conductive layers for pads and method of manufacturing thereof | Mar 29, 2007 | Issued |