Search

Tanya Theresa Ngo Motsinger

Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )

Most Active Art Unit
2637
Art Unit(s)
2635, 2613, 2637
Total Applications
469
Issued Applications
358
Pending Applications
25
Abandoned Applications
99

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4749193 [patent_doc_number] => 20080157264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Shallow trench isolation devices and methods' [patent_app_type] => utility [patent_app_number] => 11/654329 [patent_app_country] => US [patent_app_date] => 2007-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2813 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157264.pdf [firstpage_image] =>[orig_patent_app_number] => 11654329 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/654329
Method of forming an isolation structure by performing multiple high-density plasma depositions Jan 16, 2007 Issued
Array ( [id] => 4825870 [patent_doc_number] => 20080124834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Mounting method of semiconductor element and manufacturing method of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/653954 [patent_app_country] => US [patent_app_date] => 2007-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6885 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20080124834.pdf [firstpage_image] =>[orig_patent_app_number] => 11653954 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/653954
Mounting method of semiconductor element using outside connection projection electyrode and manufacturing method of semiconductor device using outside connection projection electrode Jan 16, 2007 Issued
Array ( [id] => 4805926 [patent_doc_number] => 20080169504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-17 [patent_title] => 'Semiconductor constructions, methods of forming semiconductor constructions, and methods of recessing materials within openings' [patent_app_type] => utility [patent_app_number] => 11/652863 [patent_app_country] => US [patent_app_date] => 2007-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5975 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20080169504.pdf [firstpage_image] =>[orig_patent_app_number] => 11652863 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/652863
Methods of forming semiconductor constructions, and methods of recessing materials within openings Jan 11, 2007 Issued
Array ( [id] => 5159924 [patent_doc_number] => 20070172968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Method of processing semiconductor substrate' [patent_app_type] => utility [patent_app_number] => 11/651863 [patent_app_country] => US [patent_app_date] => 2007-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2057 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20070172968.pdf [firstpage_image] =>[orig_patent_app_number] => 11651863 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/651863
Method of processing semiconductor substrate Jan 9, 2007 Abandoned
Array ( [id] => 278338 [patent_doc_number] => 07557415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Trench isolation type semiconductor device and related method of manufacture' [patent_app_type] => utility [patent_app_number] => 11/650418 [patent_app_country] => US [patent_app_date] => 2007-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 4645 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/557/07557415.pdf [firstpage_image] =>[orig_patent_app_number] => 11650418 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/650418
Trench isolation type semiconductor device and related method of manufacture Jan 7, 2007 Issued
Array ( [id] => 4971390 [patent_doc_number] => 20070111392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Method for thermally releasing chip cut piece from thermal release type pressure sensitive adhesive sheet, electronic component and circuit board' [patent_app_type] => utility [patent_app_number] => 11/650449 [patent_app_country] => US [patent_app_date] => 2007-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5629 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20070111392.pdf [firstpage_image] =>[orig_patent_app_number] => 11650449 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/650449
Method for thermally releasing chip cut piece from thermal release type pressure sensitive adhesive sheet, electronic component and circuit board Jan 7, 2007 Abandoned
Array ( [id] => 122712 [patent_doc_number] => 07709874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-04 [patent_title] => 'Semiconductor device having a split gate structure with a recessed top face electrode' [patent_app_type] => utility [patent_app_number] => 11/649208 [patent_app_country] => US [patent_app_date] => 2007-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 43 [patent_no_of_words] => 11808 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/709/07709874.pdf [firstpage_image] =>[orig_patent_app_number] => 11649208 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/649208
Semiconductor device having a split gate structure with a recessed top face electrode Jan 3, 2007 Issued
Array ( [id] => 4925214 [patent_doc_number] => 20080164577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'Patterned silicon submicron tubes' [patent_app_type] => utility [patent_app_number] => 11/649634 [patent_app_country] => US [patent_app_date] => 2007-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3860 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20080164577.pdf [firstpage_image] =>[orig_patent_app_number] => 11649634 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/649634
Patterned silicon submicron tubes Jan 3, 2007 Issued
Array ( [id] => 270418 [patent_doc_number] => 07563654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Method of manufacturing semiconductor device for formation of pin transistor' [patent_app_type] => utility [patent_app_number] => 11/647759 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3482 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/563/07563654.pdf [firstpage_image] =>[orig_patent_app_number] => 11647759 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/647759
Method of manufacturing semiconductor device for formation of pin transistor Dec 28, 2006 Issued
Array ( [id] => 204493 [patent_doc_number] => 07629213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-08 [patent_title] => 'Method of manufacturing flash memory device with void between gate patterns' [patent_app_type] => utility [patent_app_number] => 11/647628 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1385 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/629/07629213.pdf [firstpage_image] =>[orig_patent_app_number] => 11647628 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/647628
Method of manufacturing flash memory device with void between gate patterns Dec 28, 2006 Issued
Array ( [id] => 13655 [patent_doc_number] => 07803681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-28 [patent_title] => 'Semiconductor device with a bulb-type recess gate' [patent_app_type] => utility [patent_app_number] => 11/647328 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 2271 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/803/07803681.pdf [firstpage_image] =>[orig_patent_app_number] => 11647328 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/647328
Semiconductor device with a bulb-type recess gate Dec 28, 2006 Issued
Array ( [id] => 4932999 [patent_doc_number] => 20080003774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'Semiconductor device manufactured with a double shallow trench isolation process' [patent_app_type] => utility [patent_app_number] => 11/647324 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4683 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20080003774.pdf [firstpage_image] =>[orig_patent_app_number] => 11647324 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/647324
Semiconductor device manufactured with a double shallow trench isolation process Dec 28, 2006 Issued
Array ( [id] => 4772036 [patent_doc_number] => 20080057694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/646699 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2822 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20080057694.pdf [firstpage_image] =>[orig_patent_app_number] => 11646699 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/646699
Method for manufacturing semiconductor device Dec 27, 2006 Abandoned
Array ( [id] => 5085468 [patent_doc_number] => 20070275519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-29 [patent_title] => 'Method of manufacturing non-volatile memory device' [patent_app_type] => utility [patent_app_number] => 11/646728 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1953 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20070275519.pdf [firstpage_image] =>[orig_patent_app_number] => 11646728 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/646728
Method of manufacturing non-volatile memory device Dec 27, 2006 Issued
Array ( [id] => 4930440 [patent_doc_number] => 20080001215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'Semiconductor device having recess gate and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/646233 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2187 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20080001215.pdf [firstpage_image] =>[orig_patent_app_number] => 11646233 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/646233
Semiconductor device having recess gate and method of fabricating the same Dec 27, 2006 Abandoned
Array ( [id] => 5095741 [patent_doc_number] => 20070117350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'STRAINED SILICON ON INSULATOR (SSOI) WITH LAYER TRANSFER FROM OXIDIZED DONOR' [patent_app_type] => utility [patent_app_number] => 11/616517 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7609 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20070117350.pdf [firstpage_image] =>[orig_patent_app_number] => 11616517 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/616517
STRAINED SILICON ON INSULATOR (SSOI) WITH LAYER TRANSFER FROM OXIDIZED DONOR Dec 26, 2006 Abandoned
Array ( [id] => 4988700 [patent_doc_number] => 20070155039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Method for manufacturing CMOS image sensor' [patent_app_type] => utility [patent_app_number] => 11/646803 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2659 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20070155039.pdf [firstpage_image] =>[orig_patent_app_number] => 11646803 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/646803
Method for manufacturing CMOS image sensor Dec 26, 2006 Abandoned
Array ( [id] => 196571 [patent_doc_number] => 07638384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'Method of fabricating a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/616285 [patent_app_country] => US [patent_app_date] => 2006-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 1740 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/638/07638384.pdf [firstpage_image] =>[orig_patent_app_number] => 11616285 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/616285
Method of fabricating a semiconductor device Dec 25, 2006 Issued
Array ( [id] => 348729 [patent_doc_number] => 07494843 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-02-24 [patent_title] => 'Method of making a semiconductor chip assembly with thermal conductor and encapsulant grinding' [patent_app_type] => utility [patent_app_number] => 11/645488 [patent_app_country] => US [patent_app_date] => 2006-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 135 [patent_no_of_words] => 27312 [patent_no_of_claims] => 100 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/494/07494843.pdf [firstpage_image] =>[orig_patent_app_number] => 11645488 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/645488
Method of making a semiconductor chip assembly with thermal conductor and encapsulant grinding Dec 25, 2006 Issued
Array ( [id] => 190833 [patent_doc_number] => 07642144 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-05 [patent_title] => 'Transistors with recessed active trenches for increased effective gate width' [patent_app_type] => utility [patent_app_number] => 11/644259 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 5802 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/642/07642144.pdf [firstpage_image] =>[orig_patent_app_number] => 11644259 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/644259
Transistors with recessed active trenches for increased effective gate width Dec 21, 2006 Issued
Menu