
Tanya Theresa Ngo Motsinger
Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )
| Most Active Art Unit | 2637 |
| Art Unit(s) | 2635, 2613, 2637 |
| Total Applications | 469 |
| Issued Applications | 358 |
| Pending Applications | 25 |
| Abandoned Applications | 99 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4876595
[patent_doc_number] => 20080149978
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-26
[patent_title] => 'Memory device and method of fabricating a memory device'
[patent_app_type] => utility
[patent_app_number] => 11/645124
[patent_app_country] => US
[patent_app_date] => 2006-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3976
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0149/20080149978.pdf
[firstpage_image] =>[orig_patent_app_number] => 11645124
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/645124 | Memory device and method of fabricating a memory device | Dec 20, 2006 | Abandoned |
Array
(
[id] => 5213701
[patent_doc_number] => 20070102781
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-10
[patent_title] => 'Split transfer gate for dark current suppression an imager pixel'
[patent_app_type] => utility
[patent_app_number] => 11/642868
[patent_app_country] => US
[patent_app_date] => 2006-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 4697
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0102/20070102781.pdf
[firstpage_image] =>[orig_patent_app_number] => 11642868
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/642868 | Split transfer gate for dark current suppression an imager pixel | Dec 20, 2006 | Issued |
Array
(
[id] => 330428
[patent_doc_number] => 07510923
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-31
[patent_title] => 'Slim spacer implementation to improve drive current'
[patent_app_type] => utility
[patent_app_number] => 11/641578
[patent_app_country] => US
[patent_app_date] => 2006-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 17
[patent_no_of_words] => 3631
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/510/07510923.pdf
[firstpage_image] =>[orig_patent_app_number] => 11641578
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/641578 | Slim spacer implementation to improve drive current | Dec 18, 2006 | Issued |
Array
(
[id] => 5175148
[patent_doc_number] => 20070176206
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-02
[patent_title] => 'Method of manufacturing field emission device'
[patent_app_type] => utility
[patent_app_number] => 11/604731
[patent_app_country] => US
[patent_app_date] => 2006-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3415
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0176/20070176206.pdf
[firstpage_image] =>[orig_patent_app_number] => 11604731
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/604731 | Method of manufacturing field emission device | Nov 27, 2006 | Issued |
Array
(
[id] => 318589
[patent_doc_number] => 07521298
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-04-21
[patent_title] => 'Thin film transistor array panel of active liquid crystal display and fabrication method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/563196
[patent_app_country] => US
[patent_app_date] => 2006-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 4125
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 252
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/521/07521298.pdf
[firstpage_image] =>[orig_patent_app_number] => 11563196
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/563196 | Thin film transistor array panel of active liquid crystal display and fabrication method thereof | Nov 24, 2006 | Issued |
Array
(
[id] => 5095697
[patent_doc_number] => 20070117306
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-24
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/602494
[patent_app_country] => US
[patent_app_date] => 2006-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 10138
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0117/20070117306.pdf
[firstpage_image] =>[orig_patent_app_number] => 11602494
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/602494 | Cooling semiconductor device and manufacturing method thereof | Nov 20, 2006 | Issued |
Array
(
[id] => 4604635
[patent_doc_number] => 07985615
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-07-26
[patent_title] => 'Method of forming a carbon nanotube/nanowire thermo-photovoltaic cell'
[patent_app_type] => utility
[patent_app_number] => 11/561733
[patent_app_country] => US
[patent_app_date] => 2006-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3410
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/985/07985615.pdf
[firstpage_image] =>[orig_patent_app_number] => 11561733
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/561733 | Method of forming a carbon nanotube/nanowire thermo-photovoltaic cell | Nov 19, 2006 | Issued |
Array
(
[id] => 4899401
[patent_doc_number] => 20080119015
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-22
[patent_title] => 'METHOD OF PACKAGING A SEMICONDUCTOR DEVICE AND A PREFABRICATED CONNECTOR'
[patent_app_type] => utility
[patent_app_number] => 11/561063
[patent_app_country] => US
[patent_app_date] => 2006-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3456
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0119/20080119015.pdf
[firstpage_image] =>[orig_patent_app_number] => 11561063
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/561063 | Method of packaging a semiconductor device and a prefabricated connector | Nov 16, 2006 | Issued |
Array
(
[id] => 5428657
[patent_doc_number] => 20090087967
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-02
[patent_title] => 'PRECURSORS AND PROCESSES FOR LOW TEMPERATURE SELECTIVE EPITAXIAL GROWTH'
[patent_app_type] => utility
[patent_app_number] => 11/559679
[patent_app_country] => US
[patent_app_date] => 2006-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12856
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0087/20090087967.pdf
[firstpage_image] =>[orig_patent_app_number] => 11559679
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/559679 | PRECURSORS AND PROCESSES FOR LOW TEMPERATURE SELECTIVE EPITAXIAL GROWTH | Nov 13, 2006 | Abandoned |
Array
(
[id] => 5014056
[patent_doc_number] => 20070257264
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-08
[patent_title] => 'CATALYST-FREE GROWTH OF GaN NANOSCALE NEEDLES AND APPLICATION IN InGaN/GaN VISIBLE LEDS'
[patent_app_type] => utility
[patent_app_number] => 11/559214
[patent_app_country] => US
[patent_app_date] => 2006-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4807
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0257/20070257264.pdf
[firstpage_image] =>[orig_patent_app_number] => 11559214
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/559214 | CATALYST-FREE GROWTH OF GaN NANOSCALE NEEDLES AND APPLICATION IN InGaN/GaN VISIBLE LEDS | Nov 12, 2006 | Abandoned |
Array
(
[id] => 907141
[patent_doc_number] => 07332418
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-02-19
[patent_title] => 'High-density single transistor vertical memory gain cell'
[patent_app_type] => utility
[patent_app_number] => 11/557229
[patent_app_country] => US
[patent_app_date] => 2006-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 15
[patent_no_of_words] => 5214
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/332/07332418.pdf
[firstpage_image] =>[orig_patent_app_number] => 11557229
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/557229 | High-density single transistor vertical memory gain cell | Nov 6, 2006 | Issued |
Array
(
[id] => 5205183
[patent_doc_number] => 20070026665
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-01
[patent_title] => 'METHOD OF FABRICATING A DUAL DAMASCENE INTERCONNECT STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 11/535935
[patent_app_country] => US
[patent_app_date] => 2006-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5275
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0026/20070026665.pdf
[firstpage_image] =>[orig_patent_app_number] => 11535935
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/535935 | METHOD OF FABRICATING A DUAL DAMASCENE INTERCONNECT STRUCTURE | Sep 26, 2006 | Abandoned |
Array
(
[id] => 5168139
[patent_doc_number] => 20070068570
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-29
[patent_title] => 'Method for forming buried contact electrode of semiconductor device having pn junction and optoelectronic semiconductor device using the same'
[patent_app_type] => utility
[patent_app_number] => 11/526690
[patent_app_country] => US
[patent_app_date] => 2006-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5936
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0068/20070068570.pdf
[firstpage_image] =>[orig_patent_app_number] => 11526690
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/526690 | Method for forming buried contact electrode of semiconductor device having pn junction and optoelectronic semiconductor device using the same | Sep 25, 2006 | Issued |
Array
(
[id] => 4821420
[patent_doc_number] => 20080122473
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-29
[patent_title] => 'Method for improved single event latch up resistance in an integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/527374
[patent_app_country] => US
[patent_app_date] => 2006-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3545
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0122/20080122473.pdf
[firstpage_image] =>[orig_patent_app_number] => 11527374
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/527374 | Method for improved single event latch up resistance in an integrated circuit | Sep 24, 2006 | Issued |
Array
(
[id] => 277880
[patent_doc_number] => 07556954
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-07-07
[patent_title] => 'MOS transistor and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/526934
[patent_app_country] => US
[patent_app_date] => 2006-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2343
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/556/07556954.pdf
[firstpage_image] =>[orig_patent_app_number] => 11526934
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/526934 | MOS transistor and manufacturing method thereof | Sep 24, 2006 | Issued |
Array
(
[id] => 602841
[patent_doc_number] => 07432605
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-07
[patent_title] => 'Overlay mark, method for forming the same and application thereof'
[patent_app_type] => utility
[patent_app_number] => 11/533954
[patent_app_country] => US
[patent_app_date] => 2006-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3712
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/432/07432605.pdf
[firstpage_image] =>[orig_patent_app_number] => 11533954
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/533954 | Overlay mark, method for forming the same and application thereof | Sep 20, 2006 | Issued |
Array
(
[id] => 256342
[patent_doc_number] => 07576015
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-18
[patent_title] => 'Methods for manufacturing alignment layer, active device array substrate and color filter substrate'
[patent_app_type] => utility
[patent_app_number] => 11/533724
[patent_app_country] => US
[patent_app_date] => 2006-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 3756
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/576/07576015.pdf
[firstpage_image] =>[orig_patent_app_number] => 11533724
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/533724 | Methods for manufacturing alignment layer, active device array substrate and color filter substrate | Sep 19, 2006 | Issued |
Array
(
[id] => 4740091
[patent_doc_number] => 20080233744
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-25
[patent_title] => 'CARBON NANOTUBE SWITCHES FOR MEMORY, RF COMMUNICATIONS AND SENSING APPLICATIONS, AND METHODS OF MAKING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/523273
[patent_app_country] => US
[patent_app_date] => 2006-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 13047
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0233/20080233744.pdf
[firstpage_image] =>[orig_patent_app_number] => 11523273
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/523273 | Carbon nanotube switches for memory, RF communications and sensing applications, and methods of making the same | Sep 18, 2006 | Issued |
Array
(
[id] => 919677
[patent_doc_number] => 07320924
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-01-22
[patent_title] => 'Method of producing a chip-type solid electrolytic capacitor'
[patent_app_type] => utility
[patent_app_number] => 11/523417
[patent_app_country] => US
[patent_app_date] => 2006-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 17
[patent_no_of_words] => 3995
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/320/07320924.pdf
[firstpage_image] =>[orig_patent_app_number] => 11523417
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/523417 | Method of producing a chip-type solid electrolytic capacitor | Sep 18, 2006 | Issued |
Array
(
[id] => 833461
[patent_doc_number] => 07396750
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-08
[patent_title] => 'Method and structure for contacting two adjacent GMR memory bit'
[patent_app_type] => utility
[patent_app_number] => 11/533093
[patent_app_country] => US
[patent_app_date] => 2006-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 953
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/396/07396750.pdf
[firstpage_image] =>[orig_patent_app_number] => 11533093
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/533093 | Method and structure for contacting two adjacent GMR memory bit | Sep 18, 2006 | Issued |