
Tanya Theresa Ngo Motsinger
Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )
| Most Active Art Unit | 2637 |
| Art Unit(s) | 2635, 2613, 2637 |
| Total Applications | 469 |
| Issued Applications | 358 |
| Pending Applications | 25 |
| Abandoned Applications | 99 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 602795
[patent_doc_number] => 07432559
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-07
[patent_title] => 'Silicide formation on SiGe'
[patent_app_type] => utility
[patent_app_number] => 11/523683
[patent_app_country] => US
[patent_app_date] => 2006-09-19
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[pdf_file] => patents/07/432/07432559.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/523683 | Silicide formation on SiGe | Sep 18, 2006 | Issued |
Array
(
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[patent_doc_number] => 07482211
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[patent_issue_date] => 2009-01-27
[patent_title] => 'Junction leakage reduction in SiGe process by implantation'
[patent_app_type] => utility
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Array
(
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[patent_issue_date] => 2007-06-07
[patent_title] => 'Process-variation tolerant diode, standard cells including the same, tags and sensors containing the same, and methods for manufacturing the same'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/521924 | Method of manufacturing complementary diodes | Sep 14, 2006 | Issued |
Array
(
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[patent_issue_date] => 2008-05-29
[patent_title] => 'Strained semiconductor device and method of making same'
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Array
(
[id] => 4820702
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[patent_title] => 'Apparatus and method for selectively recessing spacers on multi-gate devices'
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Array
(
[id] => 5055494
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[patent_title] => 'Method for depositing ferroelectric thin films using a mixed oxidant gas'
[patent_app_type] => utility
[patent_app_number] => 11/520623
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Array
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[patent_title] => 'Method of reducing contamination by providing an etch stop layer at the substrate edge'
[patent_app_type] => utility
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[patent_app_country] => US
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Array
(
[id] => 817048
[patent_doc_number] => 07410856
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[patent_title] => 'Methods of forming vertical transistors'
[patent_app_type] => utility
[patent_app_number] => 11/522144
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[firstpage_image] =>[orig_patent_app_number] => 11522144
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/522144 | Methods of forming vertical transistors | Sep 13, 2006 | Issued |
Array
(
[id] => 5171991
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[patent_title] => 'Method of manufacturing silicon rich oxide (SRO) and semiconductor device employing SRO'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/519083 | Method of manufacturing silicon rich oxide (SRO) and semiconductor device employing SRO | Sep 11, 2006 | Issued |
Array
(
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[patent_title] => 'Porous semiconductor-based evaporator having porous and non-porous regions, the porous regions having through-holes'
[patent_app_type] => utility
[patent_app_number] => 11/530107
[patent_app_country] => US
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Array
(
[id] => 817055
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[patent_title] => 'Methods of forming and using memory cell structures'
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Array
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[id] => 432270
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[patent_title] => 'Methods for making microwave circuits'
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Array
(
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Array
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Array
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Array
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Array
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Array
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Array
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Array
(
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