Search

Tanya Theresa Ngo Motsinger

Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )

Most Active Art Unit
2637
Art Unit(s)
2635, 2613, 2637
Total Applications
469
Issued Applications
358
Pending Applications
25
Abandoned Applications
99

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4999932 [patent_doc_number] => 20070042566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'STRAINED SILICON ON INSULATOR (SSOI) STRUCTURE WITH IMPROVED CRYSTALLINITY IN THE STRAINED SILICON LAYER' [patent_app_type] => utility [patent_app_number] => 11/461653 [patent_app_country] => US [patent_app_date] => 2006-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8445 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20070042566.pdf [firstpage_image] =>[orig_patent_app_number] => 11461653 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/461653
STRAINED SILICON ON INSULATOR (SSOI) STRUCTURE WITH IMPROVED CRYSTALLINITY IN THE STRAINED SILICON LAYER Jul 31, 2006 Abandoned
Array ( [id] => 4826006 [patent_doc_number] => 20080124912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'SEMICONDUCTOR METHODS' [patent_app_type] => utility [patent_app_number] => 11/461673 [patent_app_country] => US [patent_app_date] => 2006-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 13396 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20080124912.pdf [firstpage_image] =>[orig_patent_app_number] => 11461673 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/461673
SEMICONDUCTOR METHODS Jul 31, 2006 Abandoned
Array ( [id] => 4820834 [patent_doc_number] => 20080122096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'METHODS FOR LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 11/460314 [patent_app_country] => US [patent_app_date] => 2006-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20080122096.pdf [firstpage_image] =>[orig_patent_app_number] => 11460314 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/460314
Methods for lateral current carrying capability improvement in semiconductor devices Jul 26, 2006 Issued
Array ( [id] => 5152070 [patent_doc_number] => 20070034952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'Method of manufacturing semiconductor device having impurity region under isolation region' [patent_app_type] => utility [patent_app_number] => 11/493529 [patent_app_country] => US [patent_app_date] => 2006-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 13432 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20070034952.pdf [firstpage_image] =>[orig_patent_app_number] => 11493529 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/493529
Method of manufacturing semiconductor device having impurity region under isolation region Jul 26, 2006 Issued
Array ( [id] => 837296 [patent_doc_number] => 07394113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-01 [patent_title] => 'Self-alignment scheme for a heterojunction bipolar transistor' [patent_app_type] => utility [patent_app_number] => 11/460013 [patent_app_country] => US [patent_app_date] => 2006-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3819 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/394/07394113.pdf [firstpage_image] =>[orig_patent_app_number] => 11460013 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/460013
Self-alignment scheme for a heterojunction bipolar transistor Jul 25, 2006 Issued
Array ( [id] => 5732931 [patent_doc_number] => 20060258048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'INTEGRATED CAPACITOR FOR WAFER LEVEL PACKAGING APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 11/460232 [patent_app_country] => US [patent_app_date] => 2006-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 3648 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20060258048.pdf [firstpage_image] =>[orig_patent_app_number] => 11460232 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/460232
INTEGRATED CAPACITOR FOR WAFER LEVEL PACKAGING APPLICATIONS Jul 25, 2006 Abandoned
Array ( [id] => 4820729 [patent_doc_number] => 20080122018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => ' WORK FUNCTION ADJUSTMENT ON FULLY SILICIDED (FUSI) GATE' [patent_app_type] => utility [patent_app_number] => 11/458503 [patent_app_country] => US [patent_app_date] => 2006-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1810 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20080122018.pdf [firstpage_image] =>[orig_patent_app_number] => 11458503 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/458503
Work function adjustment on fully silicided (FUSI) gate Jul 18, 2006 Issued
Array ( [id] => 7775608 [patent_doc_number] => 08120160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Integrated circuit device including a bifunctional core material in a chamber' [patent_app_type] => utility [patent_app_number] => 11/426677 [patent_app_country] => US [patent_app_date] => 2006-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 5557 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/120/08120160.pdf [firstpage_image] =>[orig_patent_app_number] => 11426677 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/426677
Integrated circuit device including a bifunctional core material in a chamber Jun 26, 2006 Issued
Array ( [id] => 5228124 [patent_doc_number] => 20070290231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'Method of manufacturing a bipolar transistor and bipolar transistor thereof' [patent_app_type] => utility [patent_app_number] => 11/454654 [patent_app_country] => US [patent_app_date] => 2006-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3184 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20070290231.pdf [firstpage_image] =>[orig_patent_app_number] => 11454654 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/454654
Method of manufacturing a bipolar transistor and bipolar transistor thereof Jun 14, 2006 Issued
Array ( [id] => 836934 [patent_doc_number] => 07393749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-01 [patent_title] => 'Charge balance field effect transistor' [patent_app_type] => utility [patent_app_number] => 11/450903 [patent_app_country] => US [patent_app_date] => 2006-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 42 [patent_no_of_words] => 9247 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/393/07393749.pdf [firstpage_image] =>[orig_patent_app_number] => 11450903 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/450903
Charge balance field effect transistor Jun 7, 2006 Issued
Array ( [id] => 5601489 [patent_doc_number] => 20060291834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Method and apparatus for thermally treating substrates' [patent_app_type] => utility [patent_app_number] => 11/446675 [patent_app_country] => US [patent_app_date] => 2006-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9119 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20060291834.pdf [firstpage_image] =>[orig_patent_app_number] => 11446675 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/446675
Method and apparatus for thermally treating substrates Jun 4, 2006 Issued
Array ( [id] => 5512074 [patent_doc_number] => 20090212378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'Method for producing a micromechanical structural element and semiconductor arrangement' [patent_app_type] => utility [patent_app_number] => 11/920660 [patent_app_country] => US [patent_app_date] => 2006-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8115 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20090212378.pdf [firstpage_image] =>[orig_patent_app_number] => 11920660 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/920660
Method for producing a micromechanical structural element and semiconductor arrangement May 18, 2006 Abandoned
Array ( [id] => 817077 [patent_doc_number] => 07410885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-12 [patent_title] => 'Method of reducing contamination by removing an interlayer dielectric from the substrate edge' [patent_app_type] => utility [patent_app_number] => 11/383903 [patent_app_country] => US [patent_app_date] => 2006-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7945 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/410/07410885.pdf [firstpage_image] =>[orig_patent_app_number] => 11383903 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/383903
Method of reducing contamination by removing an interlayer dielectric from the substrate edge May 16, 2006 Issued
Array ( [id] => 833475 [patent_doc_number] => 07396764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-08 [patent_title] => 'Manufacturing method for forming all regions of the gate electrode silicided' [patent_app_type] => utility [patent_app_number] => 11/381654 [patent_app_country] => US [patent_app_date] => 2006-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 49 [patent_no_of_words] => 9877 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/396/07396764.pdf [firstpage_image] =>[orig_patent_app_number] => 11381654 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/381654
Manufacturing method for forming all regions of the gate electrode silicided May 3, 2006 Issued
Array ( [id] => 5141864 [patent_doc_number] => 20070004080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Hermetic seals for micro-electromechanical system devices' [patent_app_type] => utility [patent_app_number] => 11/416864 [patent_app_country] => US [patent_app_date] => 2006-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5850 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20070004080.pdf [firstpage_image] =>[orig_patent_app_number] => 11416864 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/416864
Hermetic seals for micro-electromechanical system devices May 1, 2006 Issued
Array ( [id] => 817054 [patent_doc_number] => 07410862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-12 [patent_title] => 'Trench capacitor and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/380693 [patent_app_country] => US [patent_app_date] => 2006-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3275 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/410/07410862.pdf [firstpage_image] =>[orig_patent_app_number] => 11380693 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/380693
Trench capacitor and method for fabricating the same Apr 27, 2006 Issued
Array ( [id] => 5225221 [patent_doc_number] => 20070254487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'SUBMICRON DEVICE FABRICATION' [patent_app_type] => utility [patent_app_number] => 11/380593 [patent_app_country] => US [patent_app_date] => 2006-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4141 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20070254487.pdf [firstpage_image] =>[orig_patent_app_number] => 11380593 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/380593
Submicron device fabrication Apr 26, 2006 Issued
Array ( [id] => 5210590 [patent_doc_number] => 20070249174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'PATTERNING SUB-LITHOGRAPHIC FEATURES WITH VARIABLE WIDTHS' [patent_app_type] => utility [patent_app_number] => 11/379634 [patent_app_country] => US [patent_app_date] => 2006-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 5660 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20070249174.pdf [firstpage_image] =>[orig_patent_app_number] => 11379634 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/379634
Patterning sub-lithographic features with variable widths Apr 20, 2006 Issued
Array ( [id] => 8114493 [patent_doc_number] => 08158463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Process and method for manufacturing a MOS device with intercell ion implant using one or more parallel enrichment windows' [patent_app_type] => utility [patent_app_number] => 11/919570 [patent_app_country] => US [patent_app_date] => 2006-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3985 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/158/08158463.pdf [firstpage_image] =>[orig_patent_app_number] => 11919570 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/919570
Process and method for manufacturing a MOS device with intercell ion implant using one or more parallel enrichment windows Apr 18, 2006 Issued
Array ( [id] => 5675590 [patent_doc_number] => 20060180945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-17 [patent_title] => 'Forming a cap above a metal layer' [patent_app_type] => utility [patent_app_number] => 11/402777 [patent_app_country] => US [patent_app_date] => 2006-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2955 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20060180945.pdf [firstpage_image] =>[orig_patent_app_number] => 11402777 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/402777
Forming a cap above a metal layer Apr 11, 2006 Abandoned
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