Search

Tanya Theresa Ngo Motsinger

Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )

Most Active Art Unit
2637
Art Unit(s)
2635, 2613, 2637
Total Applications
469
Issued Applications
358
Pending Applications
25
Abandoned Applications
99

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5859108 [patent_doc_number] => 20060228884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'Unidirectionally conductive materials for interconnection' [patent_app_type] => utility [patent_app_number] => 11/321127 [patent_app_country] => US [patent_app_date] => 2005-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4965 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20060228884.pdf [firstpage_image] =>[orig_patent_app_number] => 11321127 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/321127
Unidirectionally conductive materials for interconnection Dec 27, 2005 Issued
Array ( [id] => 5628679 [patent_doc_number] => 20060145147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Organic light emitting display (OLED) and its fabrication method' [patent_app_type] => utility [patent_app_number] => 11/318437 [patent_app_country] => US [patent_app_date] => 2005-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3581 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20060145147.pdf [firstpage_image] =>[orig_patent_app_number] => 11318437 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/318437
Organic light emitting display (OLED) having a gas vent groove to decrease edge open failures Dec 27, 2005 Issued
Array ( [id] => 5022820 [patent_doc_number] => 20070148786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'MgO/NiFe MTJ for high performance MRAM application' [patent_app_type] => utility [patent_app_number] => 11/317388 [patent_app_country] => US [patent_app_date] => 2005-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2738 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20070148786.pdf [firstpage_image] =>[orig_patent_app_number] => 11317388 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/317388
MgO/NiFe MTJ for high performance MRAM application Dec 21, 2005 Issued
Array ( [id] => 602799 [patent_doc_number] => 07432563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-07 [patent_title] => 'Method for producing a semiconductor component and semiconductor component produced by the same' [patent_app_type] => utility [patent_app_number] => 11/314298 [patent_app_country] => US [patent_app_date] => 2005-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 27 [patent_no_of_words] => 4138 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/432/07432563.pdf [firstpage_image] =>[orig_patent_app_number] => 11314298 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/314298
Method for producing a semiconductor component and semiconductor component produced by the same Dec 20, 2005 Issued
Array ( [id] => 112393 [patent_doc_number] => 07713856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Power semiconductor laser with low divergence and low astigmatism, and method for the production thereof' [patent_app_type] => utility [patent_app_number] => 11/722662 [patent_app_country] => US [patent_app_date] => 2005-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3590 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/713/07713856.pdf [firstpage_image] =>[orig_patent_app_number] => 11722662 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/722662
Power semiconductor laser with low divergence and low astigmatism, and method for the production thereof Dec 15, 2005 Issued
Array ( [id] => 5913046 [patent_doc_number] => 20060128108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Method for forming a titanium nitride layer and method for forming a lower electrode of a MIM capacitor using the titanium nitride layer' [patent_app_type] => utility [patent_app_number] => 11/297939 [patent_app_country] => US [patent_app_date] => 2005-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3702 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20060128108.pdf [firstpage_image] =>[orig_patent_app_number] => 11297939 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/297939
Method for forming a titanium nitride layer and method for forming a lower electrode of a MIM capacitor using the titanium nitride layer Dec 8, 2005 Abandoned
Array ( [id] => 152424 [patent_doc_number] => 07683486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-23 [patent_title] => 'Electronic apparatus interconnect routing and interconnect routing method for minimizing parasitic resistance' [patent_app_type] => utility [patent_app_number] => 11/302007 [patent_app_country] => US [patent_app_date] => 2005-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4871 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/683/07683486.pdf [firstpage_image] =>[orig_patent_app_number] => 11302007 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/302007
Electronic apparatus interconnect routing and interconnect routing method for minimizing parasitic resistance Dec 8, 2005 Issued
Array ( [id] => 5093997 [patent_doc_number] => 20070115606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'METHOD AND STRUCTURE FOR CHARGE DISSIPATION IN INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/164377 [patent_app_country] => US [patent_app_date] => 2005-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6589 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20070115606.pdf [firstpage_image] =>[orig_patent_app_number] => 11164377 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/164377
Method and structure for charge dissipation in integrated circuits Nov 20, 2005 Issued
Array ( [id] => 5213675 [patent_doc_number] => 20070102755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device' [patent_app_type] => utility [patent_app_number] => 11/269303 [patent_app_country] => US [patent_app_date] => 2005-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8092 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20070102755.pdf [firstpage_image] =>[orig_patent_app_number] => 11269303 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/269303
Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device Nov 7, 2005 Issued
Array ( [id] => 5832246 [patent_doc_number] => 20060244076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Semiconductor storage device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/261537 [patent_app_country] => US [patent_app_date] => 2005-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3226 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20060244076.pdf [firstpage_image] =>[orig_patent_app_number] => 11261537 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/261537
Semiconductor storage device and method of fabricating the same Oct 30, 2005 Abandoned
Array ( [id] => 5903415 [patent_doc_number] => 20060046362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Integrated circuit devices with high and low voltage components and processes for manufacturing these devices' [patent_app_type] => utility [patent_app_number] => 11/250118 [patent_app_country] => US [patent_app_date] => 2005-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6138 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20060046362.pdf [firstpage_image] =>[orig_patent_app_number] => 11250118 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/250118
Integrated circuit devices with high and low voltage components and processes for manufacturing these devices Oct 11, 2005 Issued
Array ( [id] => 877537 [patent_doc_number] => 07358594 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-15 [patent_title] => 'Method of forming a low k polymer E-beam printable mechanical support' [patent_app_type] => utility [patent_app_number] => 11/225310 [patent_app_country] => US [patent_app_date] => 2005-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 5205 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/358/07358594.pdf [firstpage_image] =>[orig_patent_app_number] => 11225310 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/225310
Method of forming a low k polymer E-beam printable mechanical support Sep 11, 2005 Issued
Array ( [id] => 5180724 [patent_doc_number] => 20070052066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-08 [patent_title] => 'Bipolar method and structure having improved BVCEO/RCS trade-off made with depletable collector columns' [patent_app_type] => utility [patent_app_number] => 11/217304 [patent_app_country] => US [patent_app_date] => 2005-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8037 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20070052066.pdf [firstpage_image] =>[orig_patent_app_number] => 11217304 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/217304
Bipolar method and structure having improved BVCEO/RCS trade-off made with depletable collector columns Sep 1, 2005 Issued
Array ( [id] => 92985 [patent_doc_number] => 07732817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Pattern formed structure, method of forming pattern, device, electrooptical device and electronic equipment' [patent_app_type] => utility [patent_app_number] => 11/213789 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 28 [patent_no_of_words] => 13071 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/732/07732817.pdf [firstpage_image] =>[orig_patent_app_number] => 11213789 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/213789
Pattern formed structure, method of forming pattern, device, electrooptical device and electronic equipment Aug 29, 2005 Issued
Array ( [id] => 5710601 [patent_doc_number] => 20060051946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Method for realizing a hosting structure of nanometric elements' [patent_app_type] => utility [patent_app_number] => 11/215297 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4296 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20060051946.pdf [firstpage_image] =>[orig_patent_app_number] => 11215297 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/215297
Method for realizing a hosting structure of nanometric elements Aug 29, 2005 Issued
Array ( [id] => 478381 [patent_doc_number] => 07223646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-29 [patent_title] => 'Manufacturing method of semiconductor device suppressing short-channel effect' [patent_app_type] => utility [patent_app_number] => 11/192424 [patent_app_country] => US [patent_app_date] => 2005-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 5061 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/223/07223646.pdf [firstpage_image] =>[orig_patent_app_number] => 11192424 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/192424
Manufacturing method of semiconductor device suppressing short-channel effect Jul 28, 2005 Issued
Array ( [id] => 311393 [patent_doc_number] => 07528425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Semiconductor memory with charge-trapping stack arrangement' [patent_app_type] => utility [patent_app_number] => 11/193026 [patent_app_country] => US [patent_app_date] => 2005-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 12732 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/528/07528425.pdf [firstpage_image] =>[orig_patent_app_number] => 11193026 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/193026
Semiconductor memory with charge-trapping stack arrangement Jul 28, 2005 Issued
Array ( [id] => 4557515 [patent_doc_number] => 07821020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-26 [patent_title] => 'Package for light emitting device with metal base to conduct heat' [patent_app_type] => utility [patent_app_number] => 10/578150 [patent_app_country] => US [patent_app_date] => 2005-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4462 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/821/07821020.pdf [firstpage_image] =>[orig_patent_app_number] => 10578150 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/578150
Package for light emitting device with metal base to conduct heat Jul 20, 2005 Issued
11/186014 Method for making thin film semiconductor Jul 19, 2005 Abandoned
Array ( [id] => 894973 [patent_doc_number] => 07341903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-11 [patent_title] => 'Method of forming a field effect transistor having a stressed channel region' [patent_app_type] => utility [patent_app_number] => 11/177774 [patent_app_country] => US [patent_app_date] => 2005-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 12417 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/341/07341903.pdf [firstpage_image] =>[orig_patent_app_number] => 11177774 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/177774
Method of forming a field effect transistor having a stressed channel region Jul 7, 2005 Issued
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