
Tanya Theresa Ngo Motsinger
Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )
| Most Active Art Unit | 2637 |
| Art Unit(s) | 2635, 2613, 2637 |
| Total Applications | 469 |
| Issued Applications | 358 |
| Pending Applications | 25 |
| Abandoned Applications | 99 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6912460
[patent_doc_number] => 20050176218
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-11
[patent_title] => 'Method and apparatus for manufacturing net shape semiconductor wafers'
[patent_app_type] => utility
[patent_app_number] => 11/046535
[patent_app_country] => US
[patent_app_date] => 2005-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 9152
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0176/20050176218.pdf
[firstpage_image] =>[orig_patent_app_number] => 11046535
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/046535 | Method of using a setter having a recess in manufacturing a net-shape semiconductor wafer | Jan 27, 2005 | Issued |
Array
(
[id] => 534527
[patent_doc_number] => 07172966
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-06
[patent_title] => 'Method for fabricating metallic interconnects on electronic components'
[patent_app_type] => utility
[patent_app_number] => 11/046663
[patent_app_country] => US
[patent_app_date] => 2005-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2297
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/172/07172966.pdf
[firstpage_image] =>[orig_patent_app_number] => 11046663
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/046663 | Method for fabricating metallic interconnects on electronic components | Jan 27, 2005 | Issued |
Array
(
[id] => 514928
[patent_doc_number] => 07192842
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-20
[patent_title] => 'Method for bonding wafers'
[patent_app_type] => utility
[patent_app_number] => 10/905794
[patent_app_country] => US
[patent_app_date] => 2005-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 1632
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/192/07192842.pdf
[firstpage_image] =>[orig_patent_app_number] => 10905794
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/905794 | Method for bonding wafers | Jan 19, 2005 | Issued |
Array
(
[id] => 352941
[patent_doc_number] => 07491964
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-02-17
[patent_title] => 'Nitridation of STI fill oxide to prevent the loss of STI fill oxide during manufacturing process'
[patent_app_type] => utility
[patent_app_number] => 10/905683
[patent_app_country] => US
[patent_app_date] => 2005-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 23
[patent_no_of_words] => 6258
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/491/07491964.pdf
[firstpage_image] =>[orig_patent_app_number] => 10905683
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/905683 | Nitridation of STI fill oxide to prevent the loss of STI fill oxide during manufacturing process | Jan 16, 2005 | Issued |
Array
(
[id] => 616354
[patent_doc_number] => 07144765
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-12-05
[patent_title] => 'Semiconductor device with Schottky electrode including lanthanum and boron, and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/032164
[patent_app_country] => US
[patent_app_date] => 2005-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 4631
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/144/07144765.pdf
[firstpage_image] =>[orig_patent_app_number] => 11032164
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/032164 | Semiconductor device with Schottky electrode including lanthanum and boron, and manufacturing method thereof | Jan 10, 2005 | Issued |
Array
(
[id] => 6983431
[patent_doc_number] => 20050153501
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-14
[patent_title] => 'Method for fabricating image sensor'
[patent_app_type] => utility
[patent_app_number] => 11/024663
[patent_app_country] => US
[patent_app_date] => 2004-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2149
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0153/20050153501.pdf
[firstpage_image] =>[orig_patent_app_number] => 11024663
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/024663 | Method for fabricating image sensor | Dec 29, 2004 | Issued |
Array
(
[id] => 468695
[patent_doc_number] => 07232736
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-19
[patent_title] => 'Semiconductor devices with capacitors of metal/insulator/metal structure and methods for forming the same'
[patent_app_type] => utility
[patent_app_number] => 11/027056
[patent_app_country] => US
[patent_app_date] => 2004-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 4666
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/232/07232736.pdf
[firstpage_image] =>[orig_patent_app_number] => 11027056
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/027056 | Semiconductor devices with capacitors of metal/insulator/metal structure and methods for forming the same | Dec 29, 2004 | Issued |
Array
(
[id] => 5645902
[patent_doc_number] => 20060131634
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-22
[patent_title] => 'NON-VOLATILE MEMORY, NON-VOLATILE MEMORY CELL AND OPERATION THEREOF'
[patent_app_type] => utility
[patent_app_number] => 10/905194
[patent_app_country] => US
[patent_app_date] => 2004-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3543
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0131/20060131634.pdf
[firstpage_image] =>[orig_patent_app_number] => 10905194
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/905194 | NON-VOLATILE MEMORY, NON-VOLATILE MEMORY CELL AND OPERATION THEREOF | Dec 20, 2004 | Abandoned |
Array
(
[id] => 8398889
[patent_doc_number] => 08269270
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-09-18
[patent_title] => 'Power semiconductor component having a gentle turn-off behavior'
[patent_app_type] => utility
[patent_app_number] => 11/016963
[patent_app_country] => US
[patent_app_date] => 2004-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 5155
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11016963
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/016963 | Power semiconductor component having a gentle turn-off behavior | Dec 19, 2004 | Issued |
Array
(
[id] => 5908832
[patent_doc_number] => 20060124961
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-15
[patent_title] => 'Semiconductor substrate, manufacturing method thereof, and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/540263
[patent_app_country] => US
[patent_app_date] => 2004-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 9043
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0124/20060124961.pdf
[firstpage_image] =>[orig_patent_app_number] => 10540263
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/540263 | Semiconductor substrate, manufacturing method thereof, and semiconductor device | Dec 13, 2004 | Abandoned |
Array
(
[id] => 5913024
[patent_doc_number] => 20060128086
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-15
[patent_title] => 'DEVICE HAVING DUAL ETCH STOP LINER AND PROTECTIVE LAYER AND RELATED METHODS'
[patent_app_type] => utility
[patent_app_number] => 10/905024
[patent_app_country] => US
[patent_app_date] => 2004-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2476
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0128/20060128086.pdf
[firstpage_image] =>[orig_patent_app_number] => 10905024
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/905024 | Method for forming dual etch stop liner and protective layer in a semiconductor device | Dec 9, 2004 | Issued |
Array
(
[id] => 7094753
[patent_doc_number] => 20050127413
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-16
[patent_title] => 'Solid-state imaging device and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/005733
[patent_app_country] => US
[patent_app_date] => 2004-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6896
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0127/20050127413.pdf
[firstpage_image] =>[orig_patent_app_number] => 11005733
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/005733 | Solid-state imaging device and method for manufacturing the same | Dec 6, 2004 | Issued |
Array
(
[id] => 7253634
[patent_doc_number] => 20050142810
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-30
[patent_title] => 'Structure and method for III-nitride device isolation'
[patent_app_type] => utility
[patent_app_number] => 11/004146
[patent_app_country] => US
[patent_app_date] => 2004-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3949
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0142/20050142810.pdf
[firstpage_image] =>[orig_patent_app_number] => 11004146
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/004146 | Void isolated III-nitride device | Dec 2, 2004 | Issued |
Array
(
[id] => 5843593
[patent_doc_number] => 20060121681
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-08
[patent_title] => 'Method for forming halo/pocket implants through an L-shaped sidewall spacer'
[patent_app_type] => utility
[patent_app_number] => 11/002764
[patent_app_country] => US
[patent_app_date] => 2004-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4340
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0121/20060121681.pdf
[firstpage_image] =>[orig_patent_app_number] => 11002764
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/002764 | Method for forming halo/pocket implants through an L-shaped sidewall spacer | Dec 1, 2004 | Abandoned |
Array
(
[id] => 5843632
[patent_doc_number] => 20060121717
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-08
[patent_title] => 'Bonding structure and fabrication thereof'
[patent_app_type] => utility
[patent_app_number] => 11/001003
[patent_app_country] => US
[patent_app_date] => 2004-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2890
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0121/20060121717.pdf
[firstpage_image] =>[orig_patent_app_number] => 11001003
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/001003 | Bonding structure and fabrication thereof | Dec 1, 2004 | Abandoned |
Array
(
[id] => 7169267
[patent_doc_number] => 20050121792
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'Interconnection structure and method for forming the same'
[patent_app_type] => utility
[patent_app_number] => 11/000904
[patent_app_country] => US
[patent_app_date] => 2004-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 19609
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0121/20050121792.pdf
[firstpage_image] =>[orig_patent_app_number] => 11000904
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/000904 | Semiconductor device having via connecting between interconnects | Dec 1, 2004 | Issued |
Array
(
[id] => 817009
[patent_doc_number] => 07410817
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-08-12
[patent_title] => 'Liquid crystal display device including driving circuit and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 10/998844
[patent_app_country] => US
[patent_app_date] => 2004-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 55
[patent_figures_cnt] => 78
[patent_no_of_words] => 9465
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 334
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/410/07410817.pdf
[firstpage_image] =>[orig_patent_app_number] => 10998844
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/998844 | Liquid crystal display device including driving circuit and method of fabricating the same | Nov 29, 2004 | Issued |
Array
(
[id] => 7097941
[patent_doc_number] => 20050130400
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-16
[patent_title] => 'Method for manufacturing a transparent element with invisible electrodes'
[patent_app_type] => utility
[patent_app_number] => 10/998897
[patent_app_country] => US
[patent_app_date] => 2004-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1552
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0130/20050130400.pdf
[firstpage_image] =>[orig_patent_app_number] => 10998897
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/998897 | Method for manufacturing a transparent element with invisible electrodes | Nov 29, 2004 | Issued |
Array
(
[id] => 6988743
[patent_doc_number] => 20050087846
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-28
[patent_title] => ' Semiconductor packages and leadframe assemblies'
[patent_app_type] => utility
[patent_app_number] => 10/993526
[patent_app_country] => US
[patent_app_date] => 2004-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4002
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0087/20050087846.pdf
[firstpage_image] =>[orig_patent_app_number] => 10993526
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/993526 | Semiconductor packages and leadframe assemblies | Nov 17, 2004 | Issued |
Array
(
[id] => 6988815
[patent_doc_number] => 20050087888
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-28
[patent_title] => 'Method for reduced input output area'
[patent_app_type] => utility
[patent_app_number] => 10/988684
[patent_app_country] => US
[patent_app_date] => 2004-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2678
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0087/20050087888.pdf
[firstpage_image] =>[orig_patent_app_number] => 10988684
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/988684 | Method for reduced input output area | Nov 14, 2004 | Issued |