
Tanya Theresa Ngo Motsinger
Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )
| Most Active Art Unit | 2637 |
| Art Unit(s) | 2635, 2613, 2637 |
| Total Applications | 469 |
| Issued Applications | 358 |
| Pending Applications | 25 |
| Abandoned Applications | 99 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6903136
[patent_doc_number] => 20050098531
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-12
[patent_title] => 'Method of forming conductive line'
[patent_app_type] => utility
[patent_app_number] => 10/986415
[patent_app_country] => US
[patent_app_date] => 2004-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3045
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0098/20050098531.pdf
[firstpage_image] =>[orig_patent_app_number] => 10986415
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/986415 | Method of forming a conductive line | Nov 9, 2004 | Issued |
Array
(
[id] => 5805206
[patent_doc_number] => 20060091559
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-04
[patent_title] => 'Hardmask for improved reliability of silicon based dielectrics'
[patent_app_type] => utility
[patent_app_number] => 10/981233
[patent_app_country] => US
[patent_app_date] => 2004-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7132
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0091/20060091559.pdf
[firstpage_image] =>[orig_patent_app_number] => 10981233
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/981233 | Hardmask for reliability of silicon based dielectrics | Nov 3, 2004 | Issued |
Array
(
[id] => 411477
[patent_doc_number] => 07282374
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-10-16
[patent_title] => 'Method and apparatus for comparing device and non-device structures'
[patent_app_type] => utility
[patent_app_number] => 10/980517
[patent_app_country] => US
[patent_app_date] => 2004-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 5413
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/282/07282374.pdf
[firstpage_image] =>[orig_patent_app_number] => 10980517
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/980517 | Method and apparatus for comparing device and non-device structures | Nov 2, 2004 | Issued |
Array
(
[id] => 6915540
[patent_doc_number] => 20050093101
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-05
[patent_title] => 'Method of Manufacturing Nitride Substrate for Semiconductors, and Nitride Semiconductor Substrate'
[patent_app_type] => utility
[patent_app_number] => 10/904213
[patent_app_country] => US
[patent_app_date] => 2004-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 9387
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0093/20050093101.pdf
[firstpage_image] =>[orig_patent_app_number] => 10904213
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/904213 | Method of manufacturing nitride substrate for semiconductors, and nitride semiconductor substrate | Oct 28, 2004 | Issued |
Array
(
[id] => 7235131
[patent_doc_number] => 20050079681
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-14
[patent_title] => 'Deep-trench capacitor with hemispherical grain silicon surface and method for making the same'
[patent_app_type] => utility
[patent_app_number] => 10/967181
[patent_app_country] => US
[patent_app_date] => 2004-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3468
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0079/20050079681.pdf
[firstpage_image] =>[orig_patent_app_number] => 10967181
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/967181 | Deep-trench capacitor with hemispherical grain silicon surface and method for making the same | Oct 18, 2004 | Issued |
Array
(
[id] => 6971819
[patent_doc_number] => 20050037529
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-17
[patent_title] => 'Method of fabricating display device'
[patent_app_type] => utility
[patent_app_number] => 10/951072
[patent_app_country] => US
[patent_app_date] => 2004-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 8481
[patent_no_of_claims] => 84
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0037/20050037529.pdf
[firstpage_image] =>[orig_patent_app_number] => 10951072
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/951072 | Method of fabricating display device | Sep 26, 2004 | Abandoned |
Array
(
[id] => 7203676
[patent_doc_number] => 20050042798
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-24
[patent_title] => 'Method of fabricating display device'
[patent_app_type] => utility
[patent_app_number] => 10/951065
[patent_app_country] => US
[patent_app_date] => 2004-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8481
[patent_no_of_claims] => 68
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0042/20050042798.pdf
[firstpage_image] =>[orig_patent_app_number] => 10951065
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/951065 | Method of fabricating display device | Sep 26, 2004 | Abandoned |
Array
(
[id] => 6905647
[patent_doc_number] => 20050101042
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-12
[patent_title] => 'Ejection method, lens and its manufacturing method, semiconductor laser and its fabrication method, optical device and ejection device'
[patent_app_type] => utility
[patent_app_number] => 10/941867
[patent_app_country] => US
[patent_app_date] => 2004-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 10416
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0101/20050101042.pdf
[firstpage_image] =>[orig_patent_app_number] => 10941867
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/941867 | Ejection method and optical device manufacturing method for arranging nozzles in agreement with sections subject to ejection | Sep 15, 2004 | Issued |
Array
(
[id] => 5727080
[patent_doc_number] => 20060057840
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-16
[patent_title] => 'Guard ring for improved matching'
[patent_app_type] => utility
[patent_app_number] => 10/941665
[patent_app_country] => US
[patent_app_date] => 2004-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6069
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0057/20060057840.pdf
[firstpage_image] =>[orig_patent_app_number] => 10941665
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/941665 | Guard ring for improved matching | Sep 13, 2004 | Issued |
Array
(
[id] => 425450
[patent_doc_number] => 07271433
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-09-18
[patent_title] => 'High-density single transistor vertical memory gain cell'
[patent_app_type] => utility
[patent_app_number] => 10/934299
[patent_app_country] => US
[patent_app_date] => 2004-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 15
[patent_no_of_words] => 5168
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/271/07271433.pdf
[firstpage_image] =>[orig_patent_app_number] => 10934299
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/934299 | High-density single transistor vertical memory gain cell | Sep 1, 2004 | Issued |
Array
(
[id] => 5898225
[patent_doc_number] => 20060043458
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-02
[patent_title] => 'Gate coupling in floating-gate memory cells'
[patent_app_type] => utility
[patent_app_number] => 10/932954
[patent_app_country] => US
[patent_app_date] => 2004-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3588
[patent_no_of_claims] => 51
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0043/20060043458.pdf
[firstpage_image] =>[orig_patent_app_number] => 10932954
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/932954 | Gate coupling in floating-gate memory cells | Sep 1, 2004 | Issued |
Array
(
[id] => 518058
[patent_doc_number] => 07189628
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-03-13
[patent_title] => 'Fabrication of trenches with multiple depths on the same substrate'
[patent_app_type] => utility
[patent_app_number] => 10/931605
[patent_app_country] => US
[patent_app_date] => 2004-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 19
[patent_no_of_words] => 6320
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 304
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/189/07189628.pdf
[firstpage_image] =>[orig_patent_app_number] => 10931605
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/931605 | Fabrication of trenches with multiple depths on the same substrate | Aug 30, 2004 | Issued |
Array
(
[id] => 10864542
[patent_doc_number] => 08890248
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-11-18
[patent_title] => 'Bi-directional ESD protection circuit'
[patent_app_type] => utility
[patent_app_number] => 10/926916
[patent_app_country] => US
[patent_app_date] => 2004-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 4158
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10926916
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/926916 | Bi-directional ESD protection circuit | Aug 25, 2004 | Issued |
Array
(
[id] => 637858
[patent_doc_number] => 07125811
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-24
[patent_title] => 'Oxidation method for semiconductor process'
[patent_app_type] => utility
[patent_app_number] => 10/924853
[patent_app_country] => US
[patent_app_date] => 2004-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6064
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/125/07125811.pdf
[firstpage_image] =>[orig_patent_app_number] => 10924853
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/924853 | Oxidation method for semiconductor process | Aug 24, 2004 | Issued |
Array
(
[id] => 5800653
[patent_doc_number] => 20060035464
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-16
[patent_title] => 'Method of planarizing a semiconductor substrate'
[patent_app_type] => utility
[patent_app_number] => 10/917563
[patent_app_country] => US
[patent_app_date] => 2004-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4070
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0035/20060035464.pdf
[firstpage_image] =>[orig_patent_app_number] => 10917563
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/917563 | Method of planarizing a semiconductor substrate with an etching chemistry | Aug 12, 2004 | Issued |
Array
(
[id] => 503180
[patent_doc_number] => 07205625
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-17
[patent_title] => 'Junction substrate and method of bonding substrates together'
[patent_app_type] => utility
[patent_app_number] => 10/916203
[patent_app_country] => US
[patent_app_date] => 2004-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 18
[patent_no_of_words] => 8416
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/205/07205625.pdf
[firstpage_image] =>[orig_patent_app_number] => 10916203
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/916203 | Junction substrate and method of bonding substrates together | Aug 10, 2004 | Issued |
Array
(
[id] => 738729
[patent_doc_number] => 07034336
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-04-25
[patent_title] => 'Capacitorless 1-transistor DRAM cell and fabrication method'
[patent_app_type] => utility
[patent_app_number] => 10/911994
[patent_app_country] => US
[patent_app_date] => 2004-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 2581
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/034/07034336.pdf
[firstpage_image] =>[orig_patent_app_number] => 10911994
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/911994 | Capacitorless 1-transistor DRAM cell and fabrication method | Aug 4, 2004 | Issued |
Array
(
[id] => 659593
[patent_doc_number] => 07105877
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-12
[patent_title] => 'Conductive line structure'
[patent_app_type] => utility
[patent_app_number] => 10/903624
[patent_app_country] => US
[patent_app_date] => 2004-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 1891
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/105/07105877.pdf
[firstpage_image] =>[orig_patent_app_number] => 10903624
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/903624 | Conductive line structure | Jul 29, 2004 | Issued |
Array
(
[id] => 448423
[patent_doc_number] => 07250318
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-07-31
[patent_title] => 'System and method for providing automated sample preparation for plan view transmission electron microscopy'
[patent_app_type] => utility
[patent_app_number] => 10/903367
[patent_app_country] => US
[patent_app_date] => 2004-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 24
[patent_no_of_words] => 6010
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/250/07250318.pdf
[firstpage_image] =>[orig_patent_app_number] => 10903367
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/903367 | System and method for providing automated sample preparation for plan view transmission electron microscopy | Jul 29, 2004 | Issued |
Array
(
[id] => 7061266
[patent_doc_number] => 20050003627
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-06
[patent_title] => 'Method of forming a field effect transistor'
[patent_app_type] => utility
[patent_app_number] => 10/901538
[patent_app_country] => US
[patent_app_date] => 2004-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3270
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0003/20050003627.pdf
[firstpage_image] =>[orig_patent_app_number] => 10901538
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/901538 | Method of forming a field effect transistor | Jul 27, 2004 | Issued |